18d97083cSParthiban Nallathambi// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 28d97083cSParthiban Nallathambi/* 38d97083cSParthiban Nallathambi * Copyright (C) 2021 PHYTEC Messtechnik GmbH 48d97083cSParthiban Nallathambi * Author: Jens Lang <j.lang@phytec.de> 58d97083cSParthiban Nallathambi * 68d97083cSParthiban Nallathambi * Tauri-L RS232 + RS485: 78d97083cSParthiban Nallathambi * - GPIO3_20 uart4_rs485_en needs to be driven high (active) 88d97083cSParthiban Nallathambi * - GPIO3_25 RS485_DE Driver enable 98d97083cSParthiban Nallathambi */ 108d97083cSParthiban Nallathambi 118d97083cSParthiban Nallathambi#include <dt-bindings/clock/imx8mm-clock.h> 128d97083cSParthiban Nallathambi#include <dt-bindings/gpio/gpio.h> 138d97083cSParthiban Nallathambi#include "imx8mm-pinfunc.h" 148d97083cSParthiban Nallathambi 158d97083cSParthiban Nallathambi/dts-v1/; 168d97083cSParthiban Nallathambi/plugin/; 178d97083cSParthiban Nallathambi 188d97083cSParthiban Nallathambi&gpio3 { 198d97083cSParthiban Nallathambi pinctrl-names = "default"; 208d97083cSParthiban Nallathambi pinctrl-0 = <&pinctrl_gpio3_hog>; 218d97083cSParthiban Nallathambi 228d97083cSParthiban Nallathambi uart4-rs485-en-hog { 238d97083cSParthiban Nallathambi gpio-hog; 248d97083cSParthiban Nallathambi gpios = <20 GPIO_ACTIVE_HIGH>; 25*f149be46SFrank Li output-high; 268d97083cSParthiban Nallathambi line-name = "uart4_rs485_en"; 278d97083cSParthiban Nallathambi }; 288d97083cSParthiban Nallathambi}; 298d97083cSParthiban Nallathambi 308d97083cSParthiban Nallathambi/* UART2 - RS232 */ 318d97083cSParthiban Nallathambi&uart2 { 328d97083cSParthiban Nallathambi pinctrl-names = "default"; 338d97083cSParthiban Nallathambi pinctrl-0 = <&pinctrl_uart2>; 348d97083cSParthiban Nallathambi assigned-clocks = <&clk IMX8MM_CLK_UART2>; 358d97083cSParthiban Nallathambi assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 368d97083cSParthiban Nallathambi status = "okay"; 378d97083cSParthiban Nallathambi}; 388d97083cSParthiban Nallathambi 398d97083cSParthiban Nallathambi/* UART4 - RS485 */ 408d97083cSParthiban Nallathambi&uart4 { 418d97083cSParthiban Nallathambi pinctrl-names = "default"; 428d97083cSParthiban Nallathambi pinctrl-0 = <&pinctrl_uart4>; 438d97083cSParthiban Nallathambi assigned-clocks = <&clk IMX8MM_CLK_UART4>; 448d97083cSParthiban Nallathambi assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 458d97083cSParthiban Nallathambi rts-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; 468d97083cSParthiban Nallathambi linux,rs485-enabled-at-boot-time; 478d97083cSParthiban Nallathambi status = "okay"; 488d97083cSParthiban Nallathambi}; 498d97083cSParthiban Nallathambi 508d97083cSParthiban Nallathambi&iomuxc { 518d97083cSParthiban Nallathambi pinctrl_gpio3_hog: gpio3hoggrp { 528d97083cSParthiban Nallathambi fsl,pins = < 538d97083cSParthiban Nallathambi MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x49 548d97083cSParthiban Nallathambi >; 558d97083cSParthiban Nallathambi }; 568d97083cSParthiban Nallathambi 578d97083cSParthiban Nallathambi pinctrl_uart2: uart2grp { 588d97083cSParthiban Nallathambi fsl,pins = < 598d97083cSParthiban Nallathambi MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00 608d97083cSParthiban Nallathambi MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00 618d97083cSParthiban Nallathambi >; 628d97083cSParthiban Nallathambi }; 638d97083cSParthiban Nallathambi 648d97083cSParthiban Nallathambi pinctrl_uart4: uart4grp { 658d97083cSParthiban Nallathambi fsl,pins = < 668d97083cSParthiban Nallathambi MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49 678d97083cSParthiban Nallathambi MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49 688d97083cSParthiban Nallathambi MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x49 698d97083cSParthiban Nallathambi >; 708d97083cSParthiban Nallathambi }; 718d97083cSParthiban Nallathambi}; 728d97083cSParthiban Nallathambi