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/linux/Documentation/devicetree/bindings/riscv/
H A Dextensions.yaml4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
28 riscv,isa:
33 https://riscv.org/specifications/
37 Notably, riscv,isa was defined prior to the creation of the
42 insensitive, letters in the riscv,isa string must be all
48 riscv,isa-base:
56 riscv,isa-extensions:
117 encoding") of the riscv-v-spec.
182 request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
188 of riscv-j-extension.
[all …]
/linux/drivers/gpu/drm/tegra/
H A Driscv.c11 #include "riscv.h"
32 static void riscv_writel(struct tegra_drm_riscv *riscv, u32 value, u32 offset) in riscv_writel() argument
34 writel(value, riscv->regs + offset); in riscv_writel()
37 int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv) in tegra_drm_riscv_read_descriptors() argument
39 struct tegra_drm_riscv_descriptor *bl = &riscv->bl_desc; in tegra_drm_riscv_read_descriptors()
40 struct tegra_drm_riscv_descriptor *os = &riscv->os_desc; in tegra_drm_riscv_read_descriptors()
41 const struct device_node *np = riscv->dev->of_node; in tegra_drm_riscv_read_descriptors()
47 dev_err(riscv->dev, "failed to read " name ": %d\n", err); \ in tegra_drm_riscv_read_descriptors()
62 dev_err(riscv->dev, "descriptors not available\n"); in tegra_drm_riscv_read_descriptors()
69 int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address, in tegra_drm_riscv_boot_bootrom() argument
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/linux/arch/riscv/boot/dts/tenstorrent/
H A Dblackhole.dtsi16 compatible = "sifive,x280", "sifive,rocket0", "riscv";
19 mmu-type = "riscv,sv57";
20 riscv,isa-base = "rv64i";
21 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
25 compatible = "riscv,cpu-intc";
32 compatible = "sifive,x280", "sifive,rocket0", "riscv";
35 mmu-type = "riscv,sv57";
36 riscv,isa-base = "rv64i";
37 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
41 compatible = "riscv,cpu-intc";
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/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
32 riscv,isa = "rv64imac";
33 riscv,isa-base = "rv64i";
34 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
39 compatible = "riscv,cpu-intc";
44 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
56 mmu-type = "riscv,sv39";
58 riscv,isa = "rv64imafdc";
59 riscv,isa-base = "rv64i";
60 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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H A Dfu740-c000.dtsi26 compatible = "sifive,bullet0", "riscv";
33 riscv,isa = "rv64imac";
34 riscv,isa-base = "rv64i";
35 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
40 compatible = "riscv,cpu-intc";
45 compatible = "sifive,bullet0", "riscv";
57 mmu-type = "riscv,sv39";
60 riscv,isa = "rv64imafdc";
61 riscv,isa-base = "rv64i";
62 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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/linux/arch/riscv/boot/dts/andes/
H A Dqilai.dtsi20 compatible = "andestech,ax45mp", "riscv";
23 riscv,isa-base = "rv64i";
24 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
27 mmu-type = "riscv,sv39";
38 compatible = "andestech,cpu-intc", "riscv,cpu-intc";
45 compatible = "andestech,ax45mp", "riscv";
48 riscv,isa-base = "rv64i";
49 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
52 mmu-type = "riscv,sv39";
64 "riscv,cpu-intc";
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/linux/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml4 $id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
31 https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
35 const: riscv,pmu
37 riscv,event-to-mhpmevent:
54 riscv,event-to-mhpmcounters:
68 riscv,raw-event-to-mhpmcounters:
93 riscv,event-to-mhpmevent: [ "riscv,event-to-mhpmcounters" ]
103 compatible = "riscv,pmu";
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
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/linux/Documentation/devicetree/bindings/iommu/
H A Driscv,iommu.yaml4 $id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml#
22 Visit https://github.com/riscv-non-isa/riscv-iommu for more details.
31 # actually required. For non-PCIe hardware implementations 'riscv,iommu'
37 - qemu,riscv-iommu
38 - const: riscv,iommu
42 - const: riscv,pci-iommu
84 compatible = "qemu,riscv-iommu", "riscv,iommu";
104 compatible = "qemu,riscv-iommu", "riscv,iommu";
114 compatible = "qemu,riscv-iommu", "riscv,iommu";
142 compatible = "pci1efd,edf1", "riscv,pci-iommu";
/linux/arch/riscv/kernel/tests/
H A DKconfig.debug2 menu "arch/riscv/kernel Testing and Coverage"
8 bool "arch/riscv/kernel runtime Testing"
11 Enable riscv kernel runtime testing.
16 bool "KUnit test riscv module linking at runtime" if !KUNIT_ALL_TESTS
20 Enable this option to test riscv module linking at boot. This will
34 tristate "KUnit test for riscv kprobes" if !KUNIT_ALL_TESTS
39 Enable testing for riscv kprobes. Useful for riscv and/or kprobes
47 endmenu # "arch/riscv/kernel runtime Testing"
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi19 compatible = "sifive,e51", "sifive,rocket0", "riscv";
25 riscv,isa = "rv64imac";
26 riscv,isa-base = "rv64i";
27 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
34 compatible = "riscv,cpu-intc";
40 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
52 mmu-type = "riscv,sv39";
54 riscv,isa = "rv64imafdc";
55 riscv,isa-base = "rv64i";
56 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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/linux/tools/testing/selftests/riscv/
H A DREADME4 - These tests are riscv specific and so not built or run but just skipped
5 completely when env-variable ARCH is found to be different than 'riscv'.
10 $ make TARGETS=riscv kselftest-clean
11 $ make TARGETS=riscv kselftest
15 $ make -C tools/testing/selftests TARGETS=riscv \
18 or, alternatively, only specific riscv/ subtargets can be picked:
20 $ make -C tools/testing/selftests TARGETS=riscv RISCV_SUBTARGETS="mm vector" \
/linux/Documentation/devicetree/bindings/cpu/
H A Didle-states.yaml322 Documentation/devicetree/bindings/riscv/cpus.yaml
325 http://github.com/riscv/riscv-sbi-doc/riscv-sbi.adoc
370 - riscv,idle-state
381 riscv,sbi-suspend-param:
782 compatible = "riscv";
784 riscv,isa = "rv64imafdc";
785 mmu-type = "riscv,sv48";
791 compatible = "riscv,cpu-intc";
798 compatible = "riscv";
800 riscv,isa = "rv64imafdc";
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/linux/arch/riscv/boot/dts/sophgo/
H A Dcv180x-cpus.dtsi14 compatible = "thead,c906", "riscv";
23 mmu-type = "riscv,sv39";
24 riscv,isa = "rv64imafdc";
25 riscv,isa-base = "rv64i";
26 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
30 compatible = "riscv,cpu-intc";
/linux/arch/riscv/boot/dts/thead/
H A Dth1520.dtsi23 compatible = "thead,c910", "riscv";
25 riscv,isa = "rv64imafdc";
26 riscv,isa-base = "rv64i";
27 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
40 mmu-type = "riscv,sv39";
43 compatible = "riscv,cpu-intc";
50 compatible = "thead,c910", "riscv";
52 riscv,isa = "rv64imafdc";
53 riscv,isa-base = "rv64i";
54 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
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/linux/arch/riscv/kernel/
H A Dcpu.c54 if (!of_device_is_compatible(node, "riscv")) { in riscv_early_of_processor_hartid()
68 if (of_property_read_string(node, "riscv,isa-base", &isa)) in riscv_early_of_processor_hartid()
81 if (!of_property_present(node, "riscv,isa-extensions")) in riscv_early_of_processor_hartid()
84 if (of_property_match_string(node, "riscv,isa-extensions", "i") < 0 || in riscv_early_of_processor_hartid()
85 of_property_match_string(node, "riscv,isa-extensions", "m") < 0 || in riscv_early_of_processor_hartid()
86 of_property_match_string(node, "riscv,isa-extensions", "a") < 0) { in riscv_early_of_processor_hartid()
95 pr_warn("CPU with hartid=%lu is invalid: this kernel does not parse \"riscv,isa\"", in riscv_early_of_processor_hartid()
100 if (of_property_read_string(node, "riscv,isa", &isa)) { in riscv_early_of_processor_hartid()
101 pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n", in riscv_early_of_processor_hartid()
128 if (of_device_is_compatible(node, "riscv")) { in riscv_of_parent_hartid()
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/linux/drivers/clocksource/
H A Dtimer-riscv.c11 #define pr_fmt(fmt) "riscv-timer: " fmt
26 #include <clocksource/timer-riscv.h>
179 pr_err("RISCV timer registration failed [%d]\n", error); in riscv_timer_init_common()
187 "riscv-timer", &riscv_clock_event); in riscv_timer_init_common()
199 "clockevents/riscv/timer:starting", in riscv_timer_init_common()
202 pr_err("cpu hp setup state failed for RISCV timer [%d]\n", in riscv_timer_init_common()
230 child = of_find_compatible_node(NULL, NULL, "riscv,timer"); in riscv_timer_init_dt()
233 "riscv,timer-cannot-wake-cpu"); in riscv_timer_init_dt()
240 TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
/linux/Documentation/devicetree/bindings/timer/
H A Driscv,timer.yaml4 $id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
20 in Documentation/devicetree/bindings/riscv/cpus.yaml
25 - riscv,timer
31 riscv,timer-cannot-wake-cpu:
46 compatible = "riscv,timer";
/linux/Documentation/arch/riscv/
H A Dacpi.rst9 "riscv-isa-release-1239329-2023-05-23" (commit 1239329
10 ) <https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-1239329-2023-05-23>`_
H A Dhwprobe.rst95 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
223 riscv-code-size-reduction.
228 riscv-code-size-reduction.
233 riscv-code-size-reduction.
238 riscv-code-size-reduction.
246 riscv/zawrs") of riscv-isa-manual.
253 frozen at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr.
275 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
279 riscv-zabha.
282 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
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/linux/tools/testing/kunit/qemu_configs/
H A Driscv.py11 …'Please ensure that qemu-system-riscv is installed, or edit the path in "qemu_configs/riscv.py"\n')
14 QEMU_ARCH = QemuArchParams(linux_arch='riscv',
23 kernel_path='arch/riscv/boot/Image',
/linux/lib/crc/
H A DMakefile19 crc-t10dif-$(CONFIG_RISCV) += riscv/crc16_msb.o
30 crc32-$(CONFIG_RISCV) += riscv/crc32_lsb.o riscv/crc32_msb.o
41 crc64-$(CONFIG_RISCV) += riscv/crc64_lsb.o riscv/crc64_msb.o
/linux/arch/riscv/purgatory/
H A DMakefile17 $(obj)/memcpy.o: $(srctree)/arch/riscv/lib/memcpy.S FORCE
20 $(obj)/memset.o: $(srctree)/arch/riscv/lib/memset.S FORCE
23 $(obj)/strcmp.o: $(srctree)/arch/riscv/lib/strcmp.S FORCE
26 $(obj)/strlen.o: $(srctree)/arch/riscv/lib/strlen.S FORCE
29 $(obj)/strncmp.o: $(srctree)/arch/riscv/lib/strncmp.S FORCE
/linux/arch/riscv/include/asm/
H A Dgdb_xml.h13 "qXfer:features:read:riscv-64bit-cpu.xml";
19 "<xi:include href=\"riscv-64bit-cpu.xml\"/>"
25 "<feature name=\"org.gnu.gdb.riscv.cpu\">"
65 "qXfer:features:read:riscv-32bit-cpu.xml";
71 "<xi:include href=\"riscv-32bit-cpu.xml\"/>"
77 "<feature name=\"org.gnu.gdb.riscv.cpu\">"
/linux/drivers/clk/sunxi-ng/
H A DKconfig18 depends on MACH_SUN8I || RISCV || COMPILE_TEST
23 depends on MACH_SUN8I || RISCV || COMPILE_TEST
89 depends on MACH_SUN8I || ARM64 || RISCV || COMPILE_TEST
119 depends on MACH_SUN8I || ARM64 || RISCV || COMPILE_TEST
/linux/lib/crypto/
H A DKconfig20 default y if RISCV && 64BIT && TOOLCHAIN_HAS_VECTOR_CRYPTO && \
76 default y if RISCV && 64BIT && TOOLCHAIN_HAS_VECTOR_CRYPTO && \
150 default y if RISCV
166 default 2 if MIPS || RISCV
220 default y if RISCV && 64BIT && TOOLCHAIN_HAS_VECTOR_CRYPTO && \
239 default y if RISCV && 64BIT && TOOLCHAIN_HAS_VECTOR_CRYPTO && \

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