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/linux/Documentation/devicetree/bindings/iommu/
H A Driscv,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V IOMMU Architecture Implementation
10 - Tomasz Jeznach <tjeznach@rivosinc.com>
13 The RISC-V IOMMU provides memory address translation and isolation for
14 input and output devices, supporting per-device translation context,
17 It supports identical translation table format to the RISC-V address
19 Hardware uses in-memory command and fault reporting queues with wired
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/linux/drivers/iommu/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += arm/ iommufd/
3 obj-$(CONFIG_AMD_IOMMU) += amd/
4 obj-$(CONFIG_INTEL_IOMMU) += intel/
5 obj-$(CONFIG_RISCV_IOMMU) += riscv/
6 obj-$(CONFIG_GENERIC_PT) += generic_pt/fmt/
7 obj-$(CONFIG_IOMMU_API) += iommu.o
8 obj-$(CONFIG_IOMMU_SUPPORT) += iommu-pages.o
9 obj-$(CONFIG_IOMMU_API) += iommu-traces.o
10 obj-$(CONFIG_IOMMU_API) += iommu-sysfs.o
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 # The IOVA library may also be used by non-IOMMU_API users
15 bool "IOMMU Hardware Support"
26 menu "Generic IOMMU Pagetable Support"
40 sizes at both stage-1 and stage-2, as well as address spaces
41 up to 48-bits in size.
49 a series of page-table consistency checks.
58 Enable support for the ARM Short-descriptor pagetable format.
59 This supports 32-bit virtual and physical addresses mapped using
60 2-level tables with 4KB pages/1MB sections, and contiguous entries
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/linux/Documentation/devicetree/bindings/riscv/
H A Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
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/linux/drivers/gpu/drm/tegra/
H A Dnvdec.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2022, NVIDIA Corporation.
8 #include <linux/dma-mapping.h>
10 #include <linux/iommu.h>
22 #include "riscv.h"
50 /* RISC-V specific data */
51 struct tegra_drm_riscv riscv; member
63 writel(value, nvdec->regs + offset); in nvdec_writel()
71 if (nvdec->config->supports_sid && tegra_dev_iommu_get_stream_id(nvdec->dev, &stream_id)) { in nvdec_boot_falcon()
81 err = falcon_boot(&nvdec->falcon); in nvdec_boot_falcon()
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/linux/drivers/firmware/efi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
42 resource, and set aside for direct-access (device-dax) by
45 device-dax kmem facility. Say N to have the kernel treat this
83 memory before executing it. For compatibility with non-EFI loaders,
90 depends on EFI_GENERIC_STUB && !RISCV && !LOONGARCH
129 bool "Add support for Quark capsules with non-standard headers"
202 kernel. System firmware may configure the IOMMU to prevent malicious
204 firmware can't guarantee that the OS is IOMMU-aware, it will tear
205 down IOMMU configuration when ExitBootServices() is called. This
207 damage before Linux configures the IOMMU again.
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/linux/Documentation/admin-guide/
H A Dkernel-parameters.txt39 Documentation/arch/m68k/kernel-options.rst.
49 PARISC The PA-RISC architecture is enabled.
60 RISCV RISCV architecture is enabled.
64 the Documentation/scsi/ sub-directory.
83 X86-32 X86-32, aka i386 architecture is enabled.
84 X86-64 X86-64 architecture is enabled.
85 X86 Either 32-bit or 64-bit x86 (same as X86-32+X86-64)
94 KNL Is a kernel start-up parameter.
114 force -- enable ACPI if default was off
115 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
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/linux/drivers/iommu/riscv/
H A Diommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for RISC-V IOMMU implementations.
5 * Copyright © 2022-2024 Rivos Inc.
6 * Copyright © 2023 FORTH-ICS/CARV
13 #define pr_fmt(fmt) "riscv-iommu: " fmt
20 #include <linux/iommu.h>
25 #include "../iommu-pages.h"
26 #include "iommu-bits.h"
27 #include "iommu.h"
39 /* RISC-V IOMMU PPN <> PHYS address conversions, PHYS <=> PPN[53:10] */
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/linux/tools/testing/selftests/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
4 TARGETS += amd-pstate
15 TARGETS += cpu-hotplug
19 TARGETS += dmabuf-heaps
20 TARGETS += drivers/dma-buf
38 TARGETS += filesystems/mount-notify
47 TARGETS += iommu
62 TARGETS += memory-hotplug
97 TARGETS += riscv
113 TARGETS += tc-testing
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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/linux/drivers/clk/sunxi-ng/
H A Dccu-sun20i-d1.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
26 #include "ccu-sun20i-d1.h"
43 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-cpux", osc24M,
59 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ddr0", osc24M,
73 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-periph0-4x", osc24M,
82 static SUNXI_CCU_M_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
84 static SUNXI_CCU_M_HWS(pll_periph0_800M_clk, "pll-periph0-800M",
90 static CLK_FIXED_FACTOR_HWS(pll_periph0_clk, "pll-periph0",
94 static CLK_FIXED_FACTOR_HWS(pll_periph0_div3_clk, "pll-periph0-div3",
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/linux/include/acpi/
H A Dactbl2.h1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
4 * Name: actbl2.h - ACPI Table Definitions
6 * Copyright (C) 2000 - 2025, Intel Corp.
54 #define ACPI_SIG_RHCT "RHCT" /* RISC-V Hart Capabilities Table */
55 #define ACPI_SIG_RIMT "RIMT" /* RISC-V IO Mapping Table */
64 * All tables must be byte-packed to match the ACPI specification, since
74 * essentially useless for dealing with packed data in on-disk formats or
83 * AEST - Arm Error Source Table
94 /* Common Subtable header - one per Node Structure (Subtable) */
327 * AGDI - Arm Generic Diagnostic Dump and Reset Device Interface
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/linux/arch/riscv/kvm/
H A Daia_imsic.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/irqchip/riscv-imsic.h>
45 * 1) Hardware: IMSIC VS-file (vsfile_cpu >= 0)
46 * 2) Software: IMSIC SW-file (vsfile_cpu < 0)
49 /* IMSIC VS-file */
56 /* IMSIC SW-file */
244 imsic_mrif_atomic_rmw(__mrif, __ptr, __new_val, -1UL)
254 &mrif->eithreshold); in imsic_mrif_topei()
259 eix = &mrif->eix[ei]; in imsic_mrif_topei()
260 eipend[0] = imsic_mrif_atomic_read(mrif, &eix->eie[0]) & in imsic_mrif_topei()
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/linux/Documentation/virt/kvm/
H A Dapi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
24 - System ioctls: These query and set global attributes which affect the
28 - VM ioctls: These query and set attributes that affect an entire virtual
35 - vcpu ioctls: These query and set attributes that control the operation
43 - device ioctls: These query and set attributes that control the operation
92 facility that allows backward-compatible extensions to the API to be
133 -----------------------
150 -----------------
189 address used by the VM. The IPA_Bits is encoded in bits[7-0] of the
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