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/linux/Documentation/devicetree/bindings/net/
H A Dcpsw.txt2 ------------------------------------------------------
5 - compatible : Should be one of the below:-
7 "ti,am335x-cpsw" for AM335x controllers
8 "ti,am4372-cpsw" for AM437x controllers
9 "ti,dra7-cpsw" for DRA7x controllers
10 - reg : physical base address and size of the cpsw
12 - interrupts : property with a value describing the interrupt
14 - cpdma_channels : Specifies number of channels in CPDMA
15 - ale_entries : Specifies No of entries ALE can hold
16 - bd_ram_size : Specifies internal descriptor RAM size
[all …]
H A Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marcelo Schmitt <marcelo.schmitt@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
[all …]
H A Dfaraday,ftgmac100.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Po-Yu Chuang <ratbert@faraday-tech.com>
15 - const: faraday,ftgmac100
16 - items:
17 - enum:
18 - aspeed,ast2400-mac
19 - aspeed,ast2500-mac
20 - aspeed,ast2600-mac
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H A Dtesla,fsd-ethqos.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/tesla,fsd-ethqos.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Swathi K S <swathi.ks@samsung.com>
16 - $ref: snps,dwmac.yaml#
20 const: tesla,fsd-ethqos
28 interrupt-names:
30 - const: macirq
35 - description: PTP clock
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H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
[all …]
/linux/Documentation/ABI/testing/
H A Dsysfs-class-net-phydev24 This attribute contains the 32-bit PHY Identifier as reported
34 This attribute contains the 32-bit PHY Identifier as reported
51 <empty> (not available), mii, gmii, sgmii, tbi, rev-mii,
52 rmii, rgmii, rgmii-id, rgmii-rxid, rgmii-txid, rtbi, smii
53 xgmii, moca, qsgmii, trgmii, 1000base-x, 2500base-x, rxaui,
54 xaui, 10gbase-kr, unknown
70 32-bit hexadecimal number representing a bit mask of the
/linux/Documentation/devicetree/bindings/net/dsa/
H A Dbrcm,b53.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <f.fainelli@gmail.com>
18 - const: brcm,bcm5325
19 - const: brcm,bcm53101
20 - const: brcm,bcm53115
21 - const: brcm,bcm53125
22 - const: brcm,bcm53128
23 - const: brcm,bcm53134
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H A Dmicrochip,lan937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - UNGLinuxDriver@microchip.com
13 - $ref: dsa.yaml#/$defs/ethernet-ports
18 - microchip,lan9370
19 - microchip,lan9371
20 - microchip,lan9372
21 - microchip,lan9373
22 - microchip,lan9374
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H A Dmediatek,mt7530.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
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/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-l-50.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Check Point L-50 Board Description
7 /dts-v1/;
10 #include "kirkwood-6281.dtsi"
13 model = "Check Point L-50";
14 compatible = "checkpoint,l-50", "marvell,kirkwood-88f6281", "marvell,kirkwood";
23 stdout-path = &uart0;
27 pinctrl: pin-controller@10000 {
28 pinctrl-0 = <&pmx_led38 &pmx_sysrst &pmx_button29>;
29 pinctrl-names = "default";
[all …]
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
H A Ducc.txt4 - device_type : should be "network", "hldc", "uart", "transparent"
6 - compatible : could be "ucc_geth" or "fsl_atm" and so on.
7 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
8 - reg : Offset and length of the register set for the device
9 - interrupts : <a b> where a is the interrupt number and b is a
14 - pio-handle : The phandle for the Parallel I/O port configuration.
15 - port-number : for UART drivers, the port number to use, between 0 and 3.
18 CPM UART driver, the port-number is required for the QE UART driver.
19 - soft-uart : for UART drivers, if specified this means the QE UART device
20 driver should use "Soft-UART" mode, which is needed on some SOCs that have
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64-pine64-plus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include "sun50i-a64-pine64.dts"
8 compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
14 pinctrl-names = "default";
15 pinctrl-0 = <&rgmii_pins>;
16 phy-mode = "rgmii-txid";
17 phy-handle = <&ext_rgmii_phy>;
22 ext_rgmii_phy: ethernet-phy@1 {
23 compatible = "ethernet-phy-ieee802.3-c22";
34 regulator-enable-ramp-delay = <100000>;
H A Dsun50i-a64-sopine-baseboard.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 // Based on sun50i-a64-pine64.dts, which is:
6 /dts-v1/;
8 #include "sun50i-a64-sopine.dtsi"
12 compatible = "pine64,sopine-baseboard", "pine64,sopine",
13 "allwinner,sun50i-a64";
25 stdout-path = "serial0:115200n8";
28 hdmi-connector {
29 compatible = "hdmi-connector";
34 remote-endpoint = <&hdmi_out_con>;
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsa8540p-ride.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include "sa8540p-pmics.dtsi"
17 compatible = "qcom,sa8540p-ride", "qcom,sa8540p";
29 stdout-path = "serial0:115200n8";
34 regulators-0 {
35 compatible = "qcom,pm8150-rpmh-regulators";
36 qcom,pmic-id = "a";
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxl-s905d-vero4k-plus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxl-s905d.dtsi"
9 #include "meson-gx-p23x-q20x.dtsi"
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
14 compatible = "osmc,vero4k-plus", "amlogic,s905d", "amlogic,meson-gxl";
17 gpio-keys-polled {
18 compatible = "gpio-keys-polled";
19 poll-interval = <20>;
[all …]
H A Dmeson-sm1-x96-air-gbit.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "meson-sm1-ac2xx.dtsi"
10 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
13 compatible = "amediatech,x96-air-gbit", "amlogic,sm1";
17 compatible = "amlogic,axg-sound-card";
18 model = "X96-AIR";
19 audio-aux-devs = <&tdmout_b>;
20 audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
29 assigned-clocks = <&clkc CLKID_MPLL2>,
[all …]
H A Dmeson-sm1-a95xf3-air-gbit.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "meson-sm1-ac2xx.dtsi"
10 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
13 compatible = "cyx,a95xf3-air-gbit", "amlogic,sm1";
14 model = "Shenzhen CYX Industrial Co., Ltd A95XF3-AIR";
17 compatible = "amlogic,axg-sound-card";
18 model = "A95XF3-AIR";
19 audio-aux-devs = <&tdmout_b>;
20 audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
[all …]
H A Dmeson-sm1-h96-max.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "meson-sm1-ac2xx.dtsi"
10 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
13 compatible = "haochuangyi,h96-max", "amlogic,sm1";
17 compatible = "amlogic,axg-sound-card";
18 model = "H96-MAX";
19 audio-aux-devs = <&tdmout_b>;
20 audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
29 assigned-clocks = <&clkc CLKID_MPLL2>,
[all …]
H A Dmeson-g12b-bananapi-cm4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "meson-g12b-a311d.dtsi"
7 #include <dt-bindings/gpio/meson-g12a-gpio.h>
16 stdout-path = "serial0:115200n8";
19 emmc_pwrseq: emmc-pwrseq {
20 compatible = "mmc-pwrseq-emmc";
21 reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
29 sdio_pwrseq: sdio-pwrseq {
30 compatible = "mmc-pwrseq-simple";
31 reset-gpios = <&gpio GPIOAO_6 GPIO_ACTIVE_LOW>;
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dat91-sama5d3_ksz9477_evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 /dts-v1/;
9 model = "EVB-KSZ9477";
10 compatible = "microchip,sama5d3-ksz9477-evb", "atmel,sama5d36",
14 stdout-path = &dbgu;
17 reg_3v3: regulator-3v3 {
18 compatible = "regulator-fixed";
19 regulator-name = "3v3";
20 regulator-min-microvolt = <3300000>;
21 regulator-max-microvolt = <3300000>;
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsun7i-a20-lamobo-r1.dts4 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
44 #include "sun7i-a20.dtsi"
45 #include "sunxi-common-regulators.dtsi"
47 #include <dt-bindings/gpio/gpio.h>
48 #include <dt-bindings/interrupt-controller/irq.h>
52 compatible = "lamobo,lamobo-r1", "allwinner,sun7i-a20";
61 stdout-path = "serial0:115200n8";
64 hdmi-connector {
65 compatible = "hdmi-connector";
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-osd3358-sm-red.dts1 //SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2018 Octavo Systems LLC - https://www.octavosystems.com/
9 /dts-v1/;
12 #include "am335x-osd335x-common.dtsi"
13 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/display/tda998x.h>
18 model = "Octavo Systems OSD3358-SM-RED";
19 compatible = "oct,osd3358-sm-refdesign", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
23 regulator-min-microvolt = <1800000>;
24 regulator-max-microvolt = <1800000>;
[all …]
/linux/drivers/net/dsa/realtek/
H A Drtl8365mb.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch.
4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk>
5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk>
7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4
9 * can be connected to the CPU - or another PHY - via either MII, RMII, or
10 * RGMII. The switch is configured via the Realtek Simple Management Interface
15 * .-----------------------------------.
17 * UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC |
18 * UTP <---------------> Giga PHY <-> PCS <-> P1 GMAC |
[all …]
/linux/Documentation/dev-tools/
H A Dcheckpatch.rst1 .. SPDX-License-Identifier: GPL-2.0-only
27 - -q, --quiet
31 - -v, --verbose
35 - --no-tree
39 - --no-signoff
41 Disable the 'Signed-off-by' line check. The sign-off is a simple line at
43 or otherwise have the right to pass it on as an open-source patch.
47 Signed-off-by: Random J Developer <random@developer.example.org>
49 Setting this flag effectively stops a message for a missing signed-off-by
52 - --patch
[all …]
/linux/include/linux/
H A Dphy.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c
56 * Set phydev->irq to PHY_POLL if interrupts are not supported,
60 #define PHY_POLL -1
61 #define PHY_MAC_INTERRUPT -2
70 * enum phy_interface_t - Interface Mode definitions
72 * @PHY_INTERFACE_MODE_NA: Not Applicable - don't touch
74 * @PHY_INTERFACE_MODE_MII: Media-independent interface
75 * @PHY_INTERFACE_MODE_GMII: Gigabit media-independent interface
76 * @PHY_INTERFACE_MODE_SGMII: Serial gigabit media-independent interface
[all …]

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