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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ddr/
H A Djedec,lpddr2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - elpida,ECB240ABACN
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/freebsd/usr.sbin/boot0cfg/
H A Dboot0cfg.c2 * SPDX-License-Identifier: BSD-2-Clause
52 * Offsets to the parameters of the 512-byte boot block.
124 int o_and, o_or, o_e = -1; in main()
130 d_arg = m_arg = s_arg = t_arg = -1; in main()
133 while ((c = getopt(argc, argv, "Bvb:d:e:f:i:m:o:s:t:")) != -1) in main()
157 if (sscanf(optarg, "%02x%02x-%02x%02x", in main()
182 argc -= optind; in main()
189 up = B_flag || d_arg != -1 || m_arg != -1 || o_flag || s_arg != -1 in main()
190 || t_arg != -1; in main()
220 if (d_arg != -1) in main()
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/freebsd/sys/dev/mii/
H A Dmiivar.h3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
92 #define MII_TICK 1 /* once-per-second tick */
108 uint32_t mii_mpd_rev; /* the PHY's revision (MII_REV())*/
139 #define MIIF_HAVE_GTCR 0x00000040 /* has 100base-T2/1000base-T CR */
140 #define MIIF_IS_1000X 0x00000080 /* is a 1000BASE-X device */
143 #define MIIF_FORCEANEG 0x00000400 /* force auto-negotiation */
166 #define MII_OFFSET_ANY -1
167 #define MII_PHY_ANY -1
238 MIIBUS_READREG((p)->mii_dev, (p)->mii_phy, (r))
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dnvidia,tegra20-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
17 various performance-affecting settings beyond the obvious SDRAM configuration
23 const: nvidia,tegra20-emc
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/freebsd/sys/dev/dc/
H A Dif_dcreg.h1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
85 (x->dc_type == DC_TYPE_98713 || \
86 x->dc_type == DC_TYPE_98713A || \
87 x->dc_type == DC_TYPE_987x5)
90 (x->dc_type == DC_TYPE_AL981 || \
91 x->dc_type == DC_TYPE_AN983)
94 (x->dc_type == DC_TYPE_ULI_M5261 || \
95 x->dc_type == DC_TYPE_ULI_M5263)
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212reg.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
58 #define AR_ISR_RAC 0x00c0 /* ISR read-and-clear access */
59 /* Shadow copies with read-and-clear access */
97 #define AR_Q_TXE_M 0x000003FF /* Mask for TXE (QCU 0-9) */
99 #define AR_Q_TXD_M 0x000003FF /* Mask for TXD (QCU 0-9) */
169 #define AR_D0_LCL_IFS 0x1040 /* MAC DCU-specific IFS settings */
170 #define AR_D1_LCL_IFS 0x1044 /* MAC DCU-specific IFS settings */
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5211/
H A Dar5211reg.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2006 Atheros Communications, Inc.
62 /* Shadow copies with read-and-clear access */
148 #define AR_D0_LCL_IFS 0x1040 /* DCU-specific IFS settings */
149 #define AR_D1_LCL_IFS 0x1044 /* DCU-specific IFS settings */
150 #define AR_D2_LCL_IFS 0x1048 /* DCU-specific IFS settings */
151 #define AR_D3_LCL_IFS 0x104c /* DCU-specific IFS settings */
152 #define AR_D4_LCL_IFS 0x1050 /* DCU-specific IFS settings */
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300reg.h32 /* MAC Control Register - only write values of 1 have effect */
37 #define AR_CR_SWI 0x00000040 // One-shot software interrupt
47 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc)
55 /* Rx DMA Data Buffer Pointer Threshold - High and Low Priority register */
124 #define AR_RXCFG_ZLFDMA 0x00000010 // Enable DMA of zero-length frame
238 #define AR_ISR_HP_RXOK 0x00000001 // At least one frame rx on high-priority queue sans errors
239 #define AR_ISR_LP_RXOK 0x00000002 // At least one frame rx on low-priority queue sans errors
249 #define AR_ISR_MIB 0x00001000 // MIB interrupt - see MIBC
252 #define AR_ISR_RXKCM 0x00008000 // Key-cache miss interrupt
274 #define AR_ISR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9)
[all …]
/freebsd/sys/dev/msk/
H A Dif_mskreg.h5 * Version: $Revision: 2.49 $
17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
[all …]
/freebsd/share/misc/
H A Dpci_vendors5 # Date: 2025-10-18 03:15:01
8 # the PCI ID Project at https://pci-ids.ucw.cz/.
14 # (version 2 or higher) or the 3-clause BSD License.
25 # device device_name <-- single tab
26 # subvendor subdevice subsystem_name <-- two tabs
30 # This is a relabelled RTL-8139
31 8139 AT-2500TX V3 Ethernet
41 7a09 PCI-to-PCI Bridge
51 7a19 PCI-to-PCI Bridge
57 7a29 PCI-to-PCI Bridge
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