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/freebsd/crypto/openssl/crypto/sha/asm/
H A Dsha512-ia64.pl2 # Copyright 2004-2016 The OpenSSL Project Authors. All Rights Reserved.
20 # faster than gcc and >60%(!) faster than code generated by HP-UX
21 # compiler (yes, HP-UX is generating slower code, because unlike gcc,
23 # substitutes for 64-bit rotate).
26 # and HP-UX compiler - by >40% (yes, gcc won sha512_block, but lost
28 # too much. I mean it's 64 32-bit rounds vs. 80 virtually identical
29 # 64-bit ones and 1003*64/80 gives 802. Extra cycles, 2 per round,
30 # are spent on extra work to provide for 32-bit rotations. 32-bit
32 # reason lower 32 bits are deposited to upper half of 64-bit register
36 # as custom 'mux2', "parallel 32-bit add," 'padd4' and "parallel
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam57-pruss.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
9 pruss1_tm: target-module@4b226000 {
10 compatible = "ti,sysc-pruss", "ti,sysc";
13 reg-names = "rev", "sysc";
14 ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
16 ti,sysc-midle = <SYSC_IDLE_FORCE>,
19 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
24 clock-names = "fck";
25 #address-cells = <1>;
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H A Dam4372.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/am4.h>
15 interrupt-parent = <&wakeupgen>;
16 #address-cells = <1>;
17 #size-cells = <1>;
41 #address-cells = <1>;
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H A Dam33xx-l4.dtsi2 compatible = "ti,am33xx-l4-wkup", "simple-pm-bus";
3 power-domains = <&prm_wkup>;
5 clock-names = "fck";
10 reg-names = "ap", "la", "ia0", "ia1";
11 #address-cells = <1>;
12 #size-cells = <1>;
18 compatible = "simple-p
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/freebsd/share/man/man4/
H A Ddc.415 .\" 4. Neither the name of the author nor the names of any co-contributors
41 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
63 21143 itself has support for 10baseT, BNC, AUI, MII and symbol
73 Some support only MII
93 .Bl -tag -width ".Cm 10baseT/UTP"
101 Note: the built-in NWAY autonegotiation on the original PNIC 82c168
114 .Cm full-duplex
117 .Cm full-duplex
119 .Cm half-duplex
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H A Drl.415 .\" 4. Neither the name of the author nor the names of any co-contributors
41 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
60 descriptor-based data transfer mechanism.
72 whereas the 8129 uses an external PHY via an MII bus.
85 .Bl -tag -width xxxxxxxxxxxxxxxxxxxx
100 .Ar full-duplex
102 .Ar half-duplex
109 .Ar full-duplex
111 .Ar half-duplex
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/freebsd/sys/dev/mii/
H A Drgephy.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
53 #include <dev/mii/mii.h>
54 #include <dev/mii/miivar.h>
57 #include <dev/mii/rgephyreg.h>
127 /* RTL8169S do not report auto-sense; add manually. */ in rgephy_attach()
128 sc->mii_capabilities = (PHY_READ(sc, MII_BMSR) | BMSR_ANEG) & in rgephy_attach()
129 sc->mii_capmask; in rgephy_attach()
130 if (sc->mii_capabilities & BMSR_EXTSTAT) in rgephy_attach()
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H A Dmii_fdt.c1 /*-
47 #include <dev/mii/mii.h>
48 #include <dev/mii/miivar.h>
49 #include <dev/mii/mii_fdt.h>
64 {MII_CONTYPE_MII, "mii"},
69 {MII_CONTYPE_REVMII, "rev-mii"},
72 {MII_CONTYPE_RGMII_ID, "rgmii-id"},
73 {MII_CONTYPE_RGMII_RXID, "rgmii-rxid"},
74 {MII_CONTYPE_RGMII_TXID, "rgmii-txid"},
79 {MII_CONTYPE_2000BX, "2000base-x"},
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H A Dmii.c1 /* $NetBSD: mii.c,v 1.12 1999/08/03 19:41:49 drochner Exp $ */
3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
37 * MII bus layer, glues MII-capable network interface drivers to sharable
54 #include <dev/mii/mii.h>
55 #include <dev/mii/miivar.h>
92 /* MII interface */
116 device_set_desc(dev, "MII bus"); in miibus_probe()
126 struct mii_data *mii; in miibus_attach() local
130 mii = device_get_softc(dev); in miibus_attach()
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H A Dmii_physubr.c3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
51 #include <dev/mii/mii.h>
52 #include <dev/mii/miivar.h>
58 * An array of structures to map MII media types to BMCR/ANAR settings.
77 u_int mm_gtcr; /* 100base-T2 or 1000base-T CR */
87 /* 10baseT-FDX */
99 /* 100baseTX-FDX */
107 /* 1000baseX-FDX */
115 /* 1000baseT-FDX */
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/freebsd/sys/dev/etherswitch/rtl8366/
H A Drtl8366rb.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2015-2016 Hiroki Mori.
5 * Copyright (c) 2011-2012 Stefan Bethke.
55 #include <dev/mii/mii.h>
56 #include <dev/mii/miivar.h>
84 #define RTL_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
85 #define RTL_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
86 #define RTL_LOCK_ASSERT(_sc, _what) mtx_assert(&(_s)c->sc_mtx, (_what))
87 #define RTL_TRYLOCK(_sc) mtx_trylock(&(_sc)->sc_mtx)
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/freebsd/sys/dev/smc/
H A Dif_smc.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
77 #include <dev/mii/mii.h>
78 #include <dev/mii/mii_bitbang.h>
79 #include <dev/mii/miivar.h>
83 #define SMC_LOCK(sc) mtx_lock(&(sc)->smc_mtx)
84 #define SMC_UNLOCK(sc) mtx_unlock(&(sc)->smc_mtx)
85 #define SMC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->smc_mtx, MA_OWNED)
129 * MII bit-bang glue
150 bus_barrier(sc->smc_reg, BSR, 2, in smc_select_bank()
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H A Dif_smcreg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
100 #define RPCR_DPLX 0x1000 /* Put PHY in full-duplex mode */
108 #define RPCR_LED_LINK_FDX 0x3 /* Full-duplex link detected */
203 #define MD_INT 0x0080 /* MII */
213 #define MGMT_MDO 0x0001 /* MII management output */
214 #define MGMT_MDI 0x0002 /* MII management input */
215 #define MGMT_MCLK 0x0004 /* MII management clock */
216 #define MGMT_MDOE 0x0008 /* MII management output enable */
220 #define REV 0xa macro
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
19 local-mac-address:
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
31 local-mac-address property.
32 $ref: /schemas/types.yaml#/definitions/uint8-array
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/freebsd/sys/dev/sk/
H A Dif_sk.c3 /*-
4 * SPDX-License-Identifier: BSD-4-Clause
20 * 4. Neither the name of the author nor the names of any co-contributors
36 /*-
54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
55 * the SK-984x series adapters, both single port and dual port.
58 * https://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
65 * https://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
120 #include <dev/mii/mii.h>
121 #include <dev/mii/miivar.h>
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/freebsd/sys/dev/dc/
H A Dif_dc.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
42 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
72 * o MII port, for 10Mbps and 100Mbps support and NWAY
88 * All of the workalike chips use some form of MII transceiver support
91 * the cards I've seen use an MII transceiver, probably because the
125 #include <dev/mii/mii.h>
126 #include <dev/mii/mii_bitbang.h>
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/freebsd/sys/dev/usb/net/
H A Dif_mos.c1 /*-
2 * SPDX-License-Identifier: (BSD-1-Clause AND BSD-4-Clause)
19 /*-
35 /*-
51 /*-
52 * Copyright (c) 1997, 1998, 1999, 2000-2003
66 * 4. Neither the name of the author nor the names of any co-contributors
122 #include <dev/mii/mii.h>
123 #include <dev/mii/miivar.h>
231 /* MII interface */
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H A Dif_smsc.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * Microchip LAN9xxx devices (https://www.microchip.com/en-us/product/lan9500a)
32 * The LAN9500 & LAN9500A devices are stand-alone USB to Ethernet chips that
46 * ---------------------------------
51 * the Ethernet frame, this means if the frame is padded with non-zero values
89 #include <dev/mii/mii.h>
90 #include <dev/mii/miivar.h>
166 device_printf((sc)->sc_ue.ue_dev, "debug: " fmt, ##args); \
173 device_printf((sc)->sc_ue.ue_dev, "warning: " fmt, ##args)
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx51-zii-scu2-mezz.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
13 compatible = "zii,imx51-scu2-mezz", "fsl,imx51";
16 stdout-path = &uart1;
26 mdio-gpio0 = &mdio_gpio;
29 usb_vbus: regulator-usb-vbus {
30 compatible = "regulator-fixed";
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_usb_mmc_reset>;
34 startup-delay-us = <150000>;
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/freebsd/sys/dev/re/
H A Dif_re.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1997, 1998-2003
18 * 4. Neither the name of the author nor the names of any co-contributors
59 * o 64-bit DMA
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97 * (the 'S' stands for 'single-chip'). These devices have the same
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/freebsd/sys/dev/etherswitch/arswitch/
H A Darswitch.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2011-2012 Stefan Bethke.
53 #include <dev/mii/mii.h>
54 #include <dev/mii/miivar.h>
102 sc->page = -1; in arswitch_probe()
106 sc->chip_rev = (id & AR8X16_MASK_CTRL_REV_MASK); in arswitch_probe()
107 sc->chip_ver = (id & AR8X16_MASK_CTRL_VER_MASK) >> AR8X16_MASK_CTRL_VER_SHIFT; in arswitch_probe()
111 sc->sc_switchtype = AR8X16_SWITCH_AR8216; in arswitch_probe()
115 sc->sc_switchtype = AR8X16_SWITCH_AR8226; in arswitch_probe()
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/freebsd/sys/dev/bhnd/cores/chipc/
H A Dchipcreg.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
5 * Copyright (c) 2010-2015 Broadcom Corporation
10 * distributed with the Asus RT-N16 firmware source code release.
52 #define CHIPC_CORECTRL 0x08 /* rev >= 1 */
63 #define CHIPC_CHIPCTRL 0x28 /**< chip control (rev >= 11) */
64 #define CHIPC_CHIPST 0x2C /**< chip status (rev >= 11) */
77 /* siba backplane configuration broadcast (siba-only) */
81 #define CHIPC_GPIOPU 0x58 /**< pull-up mask (rev >= 20) */
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/freebsd/crypto/openssl/crypto/modes/asm/
H A Dghash-ia64.pl2 # Copyright 2010-2020 The OpenSSL Project Authors. All Rights Reserved.
19 # The module implements "4-bit" GCM GHASH function and underlying
20 # single multiplication operation in GF(2^128). "4-bit" means that it
21 # uses 256 bytes per-key table [+128 bytes shared table]. Streamed
24 # code. To anchor to something else sha1-ia64.pl module processes one
35 # But occasionally you prove yourself wrong:-) I figured out a way to
46 for (@ARGV) { $ADDP="add" if (/[\+DD|\-mlp]64/); }
48 for (@ARGV) { $big_endian=1 if (/\-DB_ENDIAN/);
49 $big_endian=0 if (/\-DL_ENDIAN/); }
58 # in scalable manner;-) Naturally assuming data in L1 cache...
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/freebsd/sys/dev/ale/
H A Dif_ale.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
63 #include <dev/mii/mii.h>
64 #include <dev/mii/miivar.h>
161 /* MII interface. */
182 { -1, 0, 0 }
187 { -1, 0, 0 }
192 { -1, 0, 0 }
197 { -1, 0, 0 }
211 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { in ale_miibus_readreg()
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/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dqcom,ebi2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 external memory (such as NAND or other memory-mapped peripherals) whereas
25 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
31 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
32 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
33 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
34 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
35 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
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