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/freebsd/contrib/ofed/infiniband-diags/src/
H A Dperfquery.c2 * Copyright (c) 2004-2009 Voltaire Inc. All rights reserved.
17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
454 static void reset_counters(int extended, int timeout, int mask, in reset_counters() argument
459 if (!performance_reset_via(pc, portid, port, mask, timeout, in reset_counters()
461 IBEXIT("perf reset"); in reset_counters()
463 if (!performance_reset_via(pc, portid, port, mask, timeout, in reset_counters()
465 IBEXIT("perf ext reset"); in reset_counters()
469 static int reset, reset_only, all_ports, loop_ports, port, extended, xmt_sl, variable
476 static void common_func(ib_portid_t * portid, int port_num, int mask, in common_func() argument
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dst,stpmic1.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - pascal Paillet <p.paillet@foss.st.com>
24 "#interrupt-cells":
27 interrupt-controller: true
36 const: st,stpmic1-onkey
40 - description: onkey-falling, happens when onkey is pressed. IT_PONKEY_F of pmic
41 - description: onkey-rising, happens when onkey is released. IT_PONKEY_R of pmic
43 interrupt-names:
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/freebsd/sys/dev/ath/ath_hal/ar5312/
H A Dar5312reg.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
33 * PCI-MAC Configuration registers (AR2315+)
35 #define AR5315_RSTIMER_BASE 0xb1000000 /* Address for reset/timer registers */
39 #define AR5315_RESET 0x0004 /* Offset of reset control register */
40 #define AR5315_SREV 0x0014 /* Offset of reset control register */
52 #define AR5315_GPIODIR_M(x) (1 << (x)) /* mask for i/o */
61 #define AR5315_WREV (-0xefbfe0) /* Revision ID register offset */
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/freebsd/sys/contrib/device-tree/Bindings/power/reset/
H A Dsyscon-reboot.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/reset/syscon-reboot.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic SYSCON mapped register reset driver
10 - Sebastian Reichel <sre@kernel.org>
13 This is a generic reset driver using syscon to map the reset register.
14 The reset is generally performed with a write to the reset register
16 mask defined in the reboot node. Default will be little endian mode, 32 bit
18 parental dt-node. So the SYSCON reboot node should be represented as a
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/freebsd/contrib/llvm-project/llvm/include/llvm/ADT/
H A DSmallBitVector.h1 //===- llvm/ADT/SmallBitVector.h - 'Normally small' bit vectors -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
30 /// This is a 'bitvector' (really, a variable-sized bit array), optimized for
31 /// the case when the array is small. It contains one pointer-sized field, which
33 /// pointer to a larger heap-allocated array when necessary. This allows normal
46 // remaining bits are used for the small-mode representation.
47 SmallNumRawBits = NumBaseBits - 1,
50 // Theoretically this is a ceil-log2. These bits are encoded in the most
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H A DBitVector.h1 //===- llvm/ADT/BitVector.h - Bit vectors -----------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
39 assert(Current != -1 && "Trying to advance past end."); in advance()
138 return const_set_bits_iterator(*this, -1); in set_bits_end()
144 /// BitVector default ctor - Creates an empty bitvector.
147 /// BitVector ctor - Creates a bitvector of specified number of bits. All
150 : Bits(NumBitWords(s), 0 - (BitWord)t), Size(s) { in NumBitWords()
155 /// empty - Tests whether there are no bits in this bitvector.
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/freebsd/sys/dev/pms/RefTisa/sallsdk/spc/
H A Dsahwreg.h2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved.
34 /* Message Unit Registers - BAR0(0x10), BAR0(win) */
36 /* i2o=1 space register offsets - MU_I2O_ENABLE */
52 /* i2o=0 space register offsets - ~MU_I2O_ENABLE */
53 #define MSGU_IBDB_SET 0x04 /* RevA - Write only, RevB - Read/Write */
58 #define MSGU_IBDB_CLEAR 0x20 /* RevB - Host not use */
85 #define V_Inbound_Doorbell_Set_Register 0x00 /* Host R/W Local INT 0x0 MSGU - Inbound D…
86 #define V_Inbound_Doorbell_Set_RegisterU 0x04 /* Host R/W Local INT 0x4 MSGU - Inbound D…
87 …Clear_Register 0x08 /* Host No access Local W, R all 0s 0x8 MSGU - Inbound Doorbell Cle…
88 …Clear_RegisterU 0x0C /* Host No access Local W, R all 0s 0xC MSGU - Inbound Doorbell Cle…
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/freebsd/sys/contrib/device-tree/Bindings/watchdog/
H A Daspeed,ast2400-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/aspeed,ast2400-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@codeconstruct.com.au>
15 - aspeed,ast2400-wdt
16 - aspeed,ast2500-wdt
17 - aspeed,ast2600-wdt
29 aspeed,reset-type:
32 - cpu
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/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dti-sysc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/ti-sysc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
16 is mostly used for interaction between module and Power, Reset and Clock
31 pattern: "^target-module(@[0-9a-f]+)?$"
35 - items:
36 - enum:
37 - ti,sysc-omap2
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H A Dti-sysc.txt20 - compatible shall be one of the following generic types:
23 "ti,sysc-omap2"
24 "ti,sysc-omap4"
25 "ti,sysc-omap4-simple"
30 "ti,sysc-omap2-timer"
31 "ti,sysc-omap4-timer"
32 "ti,sysc-omap3430-sr"
33 "ti,sysc-omap3630-sr"
34 "ti,sysc-omap4-sr"
35 "ti,sysc-omap3-sham"
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/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dst,stm32-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/st,stm32-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Fabien Dessenne <fabien.dessenne@foss.st.com>
15 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
19 const: st,stm32mp1-m4
31 reset-names:
33 - const: mcu_rst
34 - const: hold_boot
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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dlantiq,vrx200-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13 "#phy-cells":
15 description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
19 - lantiq,vrx200-pcie-phy
20 - lantiq,arx300-pcie-phy
27 - description: PHY module clock
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dxgene.txt1 Device Tree Clock bindings for APM X-Gene
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
17 - reg : shall be the physical PLL register address for the pll clock.
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/freebsd/sys/dev/al_eth/
H A Dal_init_eth_lm.c1 /*-
51 /* num of link training failures till serdes reset */
73 /* 40GBASE-LR4 and 40GBASE-SR4 are optic modules */
79 #define AL_ETH_LM_RETIMER_WAIT_FOR_LOCK 500 /* delay after retimer reset to lock (mSec) */
111 uint8_t mask; member
115 {.addr = 0x0A, .value = 0x0C, .mask = 0xff },
116 {.addr = 0x2F, .value = 0x54, .mask = 0xff },
117 {.addr = 0x31, .value = 0x20, .mask = 0xff },
118 {.addr = 0x1E, .value = 0xE9, .mask = 0xff },
119 {.addr = 0x1F, .value = 0x0B, .mask = 0xff },
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/freebsd/sys/dev/syscon/
H A Dsyscon_power.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
29 * Driver for simple syscon poweroff and reset devices. The device tree
32 * https://www.kernel.org/doc/Documentation/devicetree/bindings/power/reset/syscon-poweroff.txt
33 * https://www.kernel.org/doc/Documentation/devicetree/bindings/power/reset/syscon-reboot.txt
57 uint32_t mask; member
69 if (sc->reboot) in syscon_power_shutdown_final()
75 SYSCON_MODIFY_4(sc->regmap, sc->offset, sc->mask, in syscon_power_shutdown_final()
76 sc->value & sc->mask); in syscon_power_shutdown_final()
86 if (ofw_bus_is_compatible(dev, "syscon-poweroff")) { in syscon_power_probe()
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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dmediatek-pcie.txt4 - compatible: Should contain one of the following strings:
5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
10 "airoha,en7523-pcie"
11 - device_type: Must be "pci"
12 - reg: Base addresses and lengths of the root ports.
13 - reg-names: Names of the above areas to use during resource lookup.
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H A Dmvebu-pci.txt5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
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/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dnvidia,tegra186-gpc-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Jon Hunter <jonathanh@nvidia.com>
16 - Rajesh Gumasta <rgumasta@nvidia.com>
19 - $ref: dma-controller.yaml#
24 - const: nvidia,tegra186-gpcdma
25 - items:
26 - enum:
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra7.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12 #include <dt-bindings/clock/dra7.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
21 interrupt-parent = <&crossbar_mpu>;
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/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300reg.h32 /* MAC Control Register - only write values of 1 have effect */
37 #define AR_CR_SWI 0x00000040 // One-shot software interrupt
47 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc)
51 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000 // Mask of PCI core master request queue…
55 /* Rx DMA Data Buffer Pointer Threshold - High and Low Priority register */
109 #define AR_FTRIG 0x000003F0 // Mask for Frame trigger level
124 #define AR_RXCFG_ZLFDMA 0x00000010 // Enable DMA of zero-length frame
148 #define AR_TOPS_MASK 0x0000FFFF // Mask for timeout prescale
152 #define AR_RXNPTO_MASK 0x000003FF // Mask for no frame received timeout
156 #define AR_TXNPTO_MASK 0x000003FF // Mask for no frame transmitted timeout
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/freebsd/sys/dev/ixgbe/
H A Dixgbe_82599.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
63 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_mac_link_ops_82599()
71 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && in ixgbe_init_mac_link_ops_82599()
73 mac->ops.disable_tx_laser = in ixgbe_init_mac_link_ops_82599()
75 mac->ops.enable_tx_laser = in ixgbe_init_mac_link_ops_82599()
77 mac->ops.flap_tx_laser = ixgbe_flap_tx_laser_multispeed_fiber; in ixgbe_init_mac_link_ops_82599()
80 mac->ops.disable_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
81 mac->ops.enable_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
82 mac->ops.flap_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
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/freebsd/sys/dev/rtwn/rtl8821a/
H A Dr21a_init.c1 /*-
108 device_printf(sc->sc_dev, in r21a_power_on()
113 /* Release WLON reset. */ in r21a_power_on()
170 ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) | in r21a_power_on()
183 struct r12a_softc *rs = sc->sc_priv; in r21a_power_off()
203 device_printf(sc->sc_dev, "%s: failed to block Tx queues\n", in r21a_power_off()
213 /* Reset whole BB. */ in r21a_power_off()
216 /* Reset MAC TRX. */ in r21a_power_off()
226 /* If firmware in ram code, do reset. */ in r21a_power_off()
232 /* Reset MCU. */ in r21a_power_off()
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dhisilicon-hns-dsaf.txt4 - compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2".
5 "hisilicon,hns-dsaf-v1" is for hip05.
6 "hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612.
7 - mode: dsa fabric mode string. only support one of dsaf modes like these:
8 "2port-64vf",
9 "6port-16rss",
10 "6port-16vf",
11 "single-port".
12 - interrupts: should contain the DSA Fabric and rcb interrupt.
13 - reg: specifies base physical address(es) and size of the device registers.
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/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-sm1-x96-air-gbit.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "meson-sm1-ac2xx.dtsi"
10 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
13 compatible = "amediatech,x96-air-gbit", "amlogic,sm1";
17 compatible = "amlogic,axg-sound-card";
18 model = "X96-AIR";
19 audio-aux-devs = <&tdmout_b>;
20 audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
29 assigned-clocks = <&clkc CLKID_MPLL2>,
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H A Dmeson-sm1-a95xf3-air-gbit.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "meson-sm1-ac2xx.dtsi"
10 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
13 compatible = "cyx,a95xf3-air-gbit", "amlogic,sm1";
14 model = "Shenzhen CYX Industrial Co., Ltd A95XF3-AIR";
17 compatible = "amlogic,axg-sound-card";
18 model = "A95XF3-AIR";
19 audio-aux-devs = <&tdmout_b>;
20 audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
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