Lines Matching +full:reset +full:- +full:mask
1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
33 * PCI-MAC Configuration registers (AR2315+)
35 #define AR5315_RSTIMER_BASE 0xb1000000 /* Address for reset/timer registers */
39 #define AR5315_RESET 0x0004 /* Offset of reset control register */
40 #define AR5315_SREV 0x0014 /* Offset of reset control register */
52 #define AR5315_GPIODIR_M(x) (1 << (x)) /* mask for i/o */
61 #define AR5315_WREV (-0xefbfe0) /* Revision ID register offset */
63 #define AR5315_WREV_ID 0x000000FF /* Mask for WMAC revision info */
65 #define AR5315_WREV_REVISION 0x0000000F /* Mask for WMAN Revsion version */
67 #define AR5315_RC_BB0_CRES 0x00000002 /* Cold reset to WMAC0 & WBB0 */
68 #define AR5315_RC_BB1_CRES 0x00000200 /* Cold reset to WMAC1 & WBB1n */
69 #define AR5315_RC_WMAC0_RES 0x00000001 /* Warm reset to WMAC 0 */
70 #define AR5315_RC_WBB0_RES 0x00000002 /* Warm reset to WBB0 */
71 #define AR5315_RC_WMAC1_RES 0x00020000 /* Warm reset to WMAC1 */
72 #define AR5315_RC_WBB1_RES 0x00040000 /* Warm reset to WBB */
75 * PCI-MAC Configuration registers (AR5312)
77 #define AR5312_RSTIMER_BASE 0xbc003000 /* Address for reset/timer registers */
82 #define AR5312_RESET 0x0020 /* Offset of reset control register */
85 #define AR5312_PCICFG_LEDMODE 0x0000001c /* LED Mode mask */
118 #define AR5312_WREV_ID 0x000000FF /* Mask for WMAC revision info */
120 #define AR5312_WREV_REVISION 0x0000000F /* Mask for WMAN Revsion version */
122 #define AR5312_RC_BB0_CRES 0x00000004 /* Cold reset to WMAC0 & WBB0 */
123 #define AR5312_RC_BB1_CRES 0x00000200 /* Cold reset to WMAC1 & WBB1n */
124 #define AR5312_RC_WMAC0_RES 0x00002000 /* Warm reset to WMAC 0 */
125 #define AR5312_RC_WBB0_RES 0x00004000 /* Warm reset to WBB0 */
126 #define AR5312_RC_WMAC1_RES 0x00020000 /* Warm reset to WMAC1 */
127 #define AR5312_RC_WBB1_RES 0x00040000 /* Warm reset to WBB */