Lines Matching +full:reset +full:- +full:mask
2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved.
34 /* Message Unit Registers - BAR0(0x10), BAR0(win) */
36 /* i2o=1 space register offsets - MU_I2O_ENABLE */
52 /* i2o=0 space register offsets - ~MU_I2O_ENABLE */
53 #define MSGU_IBDB_SET 0x04 /* RevA - Write only, RevB - Read/Write */
58 #define MSGU_IBDB_CLEAR 0x20 /* RevB - Host not use */
85 #define V_Inbound_Doorbell_Set_Register 0x00 /* Host R/W Local INT 0x0 MSGU - Inbound D…
86 #define V_Inbound_Doorbell_Set_RegisterU 0x04 /* Host R/W Local INT 0x4 MSGU - Inbound D…
87 …Clear_Register 0x08 /* Host No access Local W, R all 0s 0x8 MSGU - Inbound Doorbell Cle…
88 …Clear_RegisterU 0x0C /* Host No access Local W, R all 0s 0xC MSGU - Inbound Doorbell Cle…
89 …ell_Mask_Set_Register 0x10 /* Host RO Local R/W 0x10 MSGU - Inbound Doorbell Mask Set New i…
90 …ell_Mask_Set_RegisterU 0x14 /* Host RO Local R/W 0x14 MSGU - Inbound Doorbell Mask Set New i…
91 …_Clear_Register 0x18 /* Host RO Local W, R all 0s 0x18 MSGU - Inbound Doorbell Mask Clear New…
92 …_Clear_RegisterU 0x1C /* Host RO Local W, R all 0s 0x1C MSGU - Inbound Doorbell Mask Clear New…
93 #define V_Outbound_Doorbell_Set_Register 0x20 /* Host RO Local R/W 0x20 MSGU - Outbound …
94 #define V_Outbound_Doorbell_Set_RegisterU 0x24 /* Host RO Local R/W 0x24 MSGU - Outbound …
95 #define V_Outbound_Doorbell_Clear_Register 0x28 /* Host W, R all 0s Local RO 0x28 MSGU - …
96 #define V_Outbound_Doorbell_Clear_RegisterU 0x2C /* Host W, R all 0s Local RO 0x2C MSGU - …
97 …ell_Mask_Set_Register 0x30 /* Host RW Local RO 0x30 MSGU - Outbound Doorbell Mask Set 1's s…
98 …ell_Mask_Set_RegisterU 0x34 /* Host RW Local RO 0x30 MSGU - Outbound Doorbell Mask Set 1's s…
99 …_Clear_Register 0x38 /* Host W, R all 0s Local RO 0x38 MSGU - Outbound Doorbell Mask Clear New…
100 …_Clear_RegisterU 0x3C /* Host W, R all 0s Local RO 0x38 MSGU - Outbound Doorbell Mask Clear New…
102 #define V_Scratchpad_0_Register 0x44 /* Host RO Local R/W 0x120 MSGU - Scratchpa…
103 #define V_Scratchpad_1_Register 0x48 /* Host RO Local R/W 0x128 MSGU - Scratchpa…
104 #define V_Scratchpad_2_Register 0x4C /* Host RO Local R/W 0x130 MSGU - Scratchpa…
105 #define V_Scratchpad_3_Register 0x50 /* Host RO Local R/W 0x138 MSGU - Scratchpa…
106 #define V_Host_Scratchpad_0_Register 0x54 /* Host RW Local RO 0x140 MSGU - Scratchpad…
107 #define V_Host_Scratchpad_1_Register 0x58 /* Host RW Local RO 0x148 MSGU - Scratchpad…
108 #define V_Host_Scratchpad_2_Register 0x5C /* Host RW Local RO 0x150 MSGU - Scratchpad…
109 #define V_Host_Scratchpad_3_Register 0x60 /* Host RW Local RO 0x158 MSGU - Scratchpad…
110 #define V_Host_Scratchpad_4_Register 0x64 /* Host RW Local R/W 0x160 MSGU - Scratchpa…
111 #define V_Host_Scratchpad_5_Register 0x68 /* Host RW Local R/W 0x168 MSGU - Scratchpa…
112 #define V_Scratchpad_Rsvd_0_Register 0x6C /* Host RW Local R/W 0x170 MSGU - Scratchpa…
113 #define V_Scratchpad_Rsvd_1_Register 0x70 /* Host RW Local R/W 0x178 MSGU - Scratchpa…
114 /* 0x74 - 0xFF Reserved R all 0s */
165 /* [31:8] Reserved -- Reserved Host R / Local R/W */
167 /* Indicator that a controller soft reset has occurred.
168 The bootloader sets this field when a soft reset occurs. Host is read only.
170 b00: No soft reset occurred. Device reset value.
171 b01: Normal soft reset occurred.
172 b10: Soft reset HDA mode occurred.
173 b11: Chip reset occurred.
174 Soft Reset Occurred SFT_RST_OCR
175 [5:2] Reserved -- Reserved b0000 Reserved
177 The controller soft reset type that is required by the host side. The host sets this field and the …
178 b00: Ready for soft reset / normal status.
179 b01: Normal soft reset.
180 b10: Soft reset HDA mode.
181 b11: Chip reset.
182 Soft Reset Requested
190 /***** RevB - ODAR - Outbound DoorBell Auto-Clearing Register
191 ICT - Interrupt Coalescing Timer Register
192 ICC - Interrupt Coalescing Control Register
193 - BAR2(0x18), BAR1(win) *****/
200 #define MSGU_XCBI_IBDB_REG 0x003034 /* PCIE - Message Unit Inbound Doorbell r…
201 #define MSGU_XCBI_OBDB_REG 0x003354 /* PCIE - Message Unit Outbound Doorbell …
202 …XCBI_OBDB_MASK 0x003358 /* PCIE - Message Unit Outbound Doorbell Interrupt Ma…
203 #define MSGU_XCBI_OBDB_CLEAR 0x00303C /* PCIE - Message Unit Outbound Doorbell …
208 #define RB6_MAGIC_NUMBER_RST 0x1234 /* Magic number of soft reset for RB6 */
223 #define ODMR_MASK_ALL 0xFFFFFFFF /* mask all interrupt vector */
226 #define ODCR_CLEAR_ALL 0xFFFFFFFF /* mask all interrupt vector */
234 #define IBDB_MPIIU 0x08 /* Inbound doorbell bit3 - Unfreeze */
235 #define IBDB_MPIIF 0x04 /* Inbound doorbell bit2 - Freeze */
236 #define IBDB_MPICT 0x02 /* Inbound doorbell bit1 - Terminatio…
237 #define IBDB_MPIINI 0x01 /* Inbound doorbell bit0 - Initializa…
239 /* bit mask definition for Scratch Pad0 register */
240 #define SCRATCH_PAD0_BAR_MASK 0xFC000000 /* bit31-26 - mask bar */
241 #define SCRATCH_PAD0_OFFSET_MASK 0x03FFFFFF /* bit25-0 - offset mask */
245 #define SCRATCH_PAD1_POR 0x00 /* power on reset state */
246 #define SCRATCH_PAD1_SFR 0x01 /* soft reset state */
249 #define SCRATCH_PAD1_RST 0x04 /* soft reset toggle flag */
250 #define SCRATCH_PAD1_AAP1RDY_RST 0x08 /* AAP1 ready for soft reset */
251 …H_PAD1_STATE_MASK 0xFFFFFFF0 /* ScratchPad1 Mask other bits 31:4, bit1-0 State …
264 #define SCRATCH_PAD1_V_BOOTSTATE_HDA_SOFTRESET 0x00000030 /* HDA Mode Soft Reset */
278 #define SCRATCH_PAD1_V_RESERVED 0xFFFFC000 /* 14-31 */
326 #define SCRATCH_PAD2_SFR 0x01 /* soft reset state */
329 #define SCRATCH_PAD2_FWRDY_RST 0x04 /* FW ready for soft reset rdy flag */
330 #define SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */
331 …AD2_STATE_MASK 0xFFFFFFF0 /* ScratchPad 2 Mask for other bits 31:4, bit1-0 Stat…
377 #define SCRATCH_PAD_ERROR_MASK 0xFFFFFF00 /* Error mask bits 31:8 */
378 #define SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits 1:0 */
412 /* Dynamic map through Bar4 - 0x00700000 */
423 #define SPC_SOFT_RESET_SIGNATURE 0x252acbcd /* Signature for Soft Reset */
424 #define SPC_HDASOFT_RESET_SIGNATURE 0xa5aa27d7 /* Signature for HDA Soft Reset witho…
426 /**** SPC Top-level Registers definition for Soft Reset/HDA mode ****/
428 /* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */
429 #define SPC_REG_RESET 0x000000 /* reset register */
435 /* NMI register - BAR4(0x20), BAR2(win) 0x060000/0x070000 */
441 /* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */
447 /* PCIe Message Unit Configuration Registers offset - BAR2(0x18), BAR1(win) 0x010000 */
474 /* bit definition for SPC Device Revision register - BAR1 */
479 /* bit definition for SPC_REG_TOP_DEVICE_ID - BAR2 */
497 /* PHY Error Count Registers - BAR4(0x20), BAR2(win) (need dynamic mapping) */
513 /* PHY Error Count Control Registers - BAR2(0x18), BAR1(win) */
518 /* registers for BAR Shifting - BAR2(0x18), BAR1(win) */
534 /* 1024KB - by default */
634 /* Scratchpad Reg: bit[31]: 1-CMDFlag 0-RSPFlag; bit[30,24]:CMD/RSP; bit[23,0]:Offset/Size - Shared…