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/linux/Documentation/devicetree/bindings/gpio/
H A Dnxp,pcf8575.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nxp,pcf8575.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PCF857x-compatible I/O expanders
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be
14 driven high by a pull-up current source or driven low to ground. This
19 since the chip came out of reset (if any). The only reliable solution for
25 - maxim,max7328
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H A Dgpio-consumer-common.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-consumer-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common GPIO lines
10 - Bartosz Golaszewski <brgl@bgdev.pl>
11 - Linus Walleij <linus.walleij@linaro.org>
14 Pay attention to using proper GPIO flag (e.g. GPIO_ACTIVE_LOW) for the GPIOs
20 enable-gpios:
23 GPIO connected to the enable control pin.
[all …]
H A Dexar,xra1403.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/exar,xra1403.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: XRA1403 16-bit GPIO Expander with Reset Input
10 - Nandor Han <nandor.han@ge.com>
13 The XRA1403 is an 16-bit GPIO expander with an SPI interface. Features
16 - Individually programmable inputs:
17 - Internal pull-up resistors
18 - Polarity inversion
[all …]
/linux/Documentation/devicetree/bindings/power/reset/
H A Dgpio-restart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO controlled reset
10 - Sebastian Reichel <sre@kernel.org>
13 Drive a GPIO line that can be used to restart the system from a restart handler.
15 This binding supports level and edge triggered reset. At driver load time, the driver will
16 request the given gpio line and install a restart handler. If the optional properties
17 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Daltera-a10sr.txt4 - compatible : "altr,a10sr"
5 - spi-max-frequency : Maximum SPI frequency.
6 - reg : The SPI Chip Select address for the Arria10
8 - interrupts : The interrupt line the device is connected to.
9 - interrupt-controller : Marks the device node as an interrupt controller.
10 - #interrupt-cells : The number of cells to describe an IRQ, should be 2.
13 masks from ../interrupt-controller/interrupts.txt.
15 The A10SR consists of these sub-devices:
18 ------ ----------
19 a10sr_gpio GPIO Controller
[all …]
H A Dadi,adp5585.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
14 matrix decoder, programmable logic, reset generator, and PWM generator.
19 - items:
20 - enum:
21 - adi,adp5585-00 # Default
22 - adi,adp5585-01 # 11 GPIOs
23 - adi,adp5585-02 # No pull-up resistors by default on special pins
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-385-clearfog-gtr.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
9 SERDES mapping -
10 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
12 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
14 4. mini PCIe CON2 - PCIe2
17 USB 2.0 mapping -
18 0. USB 2.0 - 0 USB pins header CON12
19 1. USB 2.0 - 1 mini PCIe CON2
20 2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3798cv200.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
8 #include <dt-bindings/clock/histb-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/reset/ti-syscon.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8040-clearfog-gt-8k.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include "armada-8040.dtsi"
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/gpio/gpio.h>
16 compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
17 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 stdout-path = "serial0:115200n8";
35 compatible = "pwm-fan";
37 cooling-levels = <0 51 102 153 204 255>;
38 #cooling-cells = <2>;
[all …]
/linux/arch/arm/boot/dts/st/
H A Dste-hrefv60plus.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012 ST-Ericsson AB
6 #include "ste-href.dtsi"
9 model = "ST-Ericsson HREF (v60+) platform with Device Tree";
10 compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
12 thermal-zones {
13 chassis-thermal {
15 polling-delay = <20000>;
17 polling-delay-passive = <2000>;
19 thermal-sensors = <&therm1>, <&therm2>;
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Drealtek,rt5677.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Animesh Agarwal <animeshagarwal28@gmail.com>
30 - $ref: dai-common.yaml#
42 gpio-controller: true
44 '#gpio-cells':
47 realtek,pow-ldo2-gpio:
51 realtek,reset-gpio:
53 description: CODEC's RESET pin. Active low.
[all …]
H A Dnvidia,tegra20-ac97.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-ac97.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra20-ac97
23 reset-names:
35 dma-names:
37 - const: rx
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H A Dadi,adau1701.txt5 - compatible: Should contain "adi,adau1701"
6 - reg: The i2c address. Value depends on the state of ADDR0
11 - reset-gpio: A GPIO spec to define which pin is connected to the
12 chip's !RESET pin. If specified, the driver will
13 assert a hardware reset at probe time.
14 - adi,pll-mode-gpios: An array of two GPIO specs to describe the GPIOs
19 - adi,pin-config: An array of 12 numerical values selecting one of the
23 - avdd-supply: Power supply for AVDD, providing 3.3V
24 - dvdd-supply: Power supply for DVDD, providing 3.3V
32 reset-gpio = <&gpio 23 0>;
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-pwrseq-emmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-emmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple eMMC hardware reset provider
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 The purpose of this driver is to perform standard eMMC hw reset
19 doesn't have hardware reset logic connected to emmc card and (limited or
25 const: mmc-pwrseq-emmc
27 reset-gpios:
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/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <1>;
23 stdout-path = "serial0:115200n8";
27 #address-cells = <1>;
28 #size-cells = <0>;
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dmotorola,mapphone-mdm6600.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/motorola,mapphone-mdm6600.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
15 - const: motorola,mapphone-mdm6600
17 enable-gpios:
18 description: GPIO to enable the USB PHY
21 power-gpios:
22 description: GPIO to power on the device
[all …]
/linux/Documentation/devicetree/bindings/net/ieee802154/
H A Dcc2520.txt4 - compatible: should be "ti,cc2520"
5 - spi-max-frequency: maximal bus speed (8000000), should be set to 4000000 depends
7 - reg: the chipselect index
8 - pinctrl-0: pin control group to be used for this controller.
9 - pinctrl-names: must contain a "default" entry.
10 - fifo-gpio: GPIO spec for the FIFO pin
11 - fifop-gpio: GPIO spec for the FIFOP pin
12 - sfd-gpio: GPIO spec for the SFD pin
13 - cca-gpio: GPIO spec for the CCA pin
14 - vreg-gpio: GPIO spec for the VREG pin
[all …]
H A Dca8210.txt4 - compatible: Should be "cascoda,ca8210"
5 - reg: Controlling chip select
6 - spi-max-frequency: Maximum clock speed, should be *less than*
8 - spi-cpol: Requires inverted clock polarity
9 - reset-gpio: GPIO attached to reset
10 - irq-gpio: GPIO attached to IRQ
12 - extclock-enable: Include for the ca8210 to route its 16MHz clock
14 - extclock-freq: Frequency in Hz of the external clock
15 - extclock-gpio: GPIO of the ca8210 to output the clock on
21 spi-max-frequency = <3000000>;
[all …]
/linux/arch/arm/mach-pxa/
H A Dreset.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/gpio.h>
7 #include <asm/proc-fns.h>
10 #include "regs-ost.h"
11 #include "reset.h"
17 static int reset_gpio = -1;
19 int init_gpio_reset(int gpio, int output, int level) in init_gpio_reset() argument
23 rc = gpio_request(gpio, "reset generator"); in init_gpio_reset()
30 rc = gpio_direction_output(gpio, level); in init_gpio_reset()
32 rc = gpio_direction_input(gpio); in init_gpio_reset()
[all …]
H A Dreset.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #define RESET_STATUS_HARDWARE (1 << 0) /* Hardware Reset */
6 #define RESET_STATUS_WATCHDOG (1 << 1) /* Watchdog Reset */
8 #define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */
15 * init_gpio_reset() - register GPIO as reset generator
16 * @gpio: gpio nr
17 * @output: set gpio as output instead of input during normal work
20 extern int init_gpio_reset(int gpio, int output, int level);
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3568-nanopi-r5s.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
9 /dts-v1/;
10 #include "rk3568-nanopi-r5s.dtsi"
14 compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
20 gpio-keys {
21 compatible = "gpio-keys";
22 pinctrl-0 = <&gpio4_a0_k1_pin>;
23 pinctrl-names = "default";
25 button-reset {
26 debounce-interval = <50>;
[all …]
/linux/drivers/reset/
H A Dreset-gpio.c1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/gpio/consumer.h>
8 #include <linux/reset-controller.h>
12 struct gpio_desc *reset; member
25 gpiod_set_value_cansleep(priv->reset, 1); in reset_gpio_assert()
35 gpiod_set_value_cansleep(priv->reset, 0); in reset_gpio_deassert()
44 return gpiod_get_value_cansleep(priv->reset); in reset_gpio_status()
56 return reset_spec->args[0]; in reset_gpio_of_xlate()
66 struct device *dev = &pdev->dev; in reset_gpio_probe()
72 return -EINVAL; in reset_gpio_probe()
[all …]
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Reset Controller framework
14 #include <linux/gpio/driver.h>
15 #include <linux/gpio/machine.h>
21 #include <linux/reset.h>
22 #include <linux/reset-controller.h>
37 * struct reset_control - a reset control
38 * @rcdev: a pointer to the reset controller device
39 * this reset control belongs to
40 * @list: list entry for the rcdev's reset controller list
[all …]
/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmediatek,mt7530.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
[all …]
/linux/Documentation/devicetree/bindings/firmware/xilinx/
H A Dxlnx,zynqmp-firmware.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24 const: xlnx,zynqmp-firmware
26 - description: For implementations complying for Versal.
27 const: xlnx,versal-firmware
[all …]

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