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/linux/arch/arm/boot/dts/st/
H A Dstm32mp151c-mect1s.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
10 #include "stm32mp15-pinctrl.dtsi"
11 #include "stm32mp15xxaa-pinctrl.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/leds/common.h>
21 stdout-path = "serial0:1500000n8";
33 v3v3: regulator-v3v3 {
34 compatible = "regulator-fixed";
[all …]
H A Dstm32mp151a-prtt1c.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
8 #include "stm32mp151a-prtt1l.dtsi"
14 clock_ksz9031: clock-ksz9031 {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <25000000>;
20 clock_sja1105: clock-sja1105 {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
[all …]
H A Dstm32mp151a-prtt1a.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
8 #include "stm32mp151a-prtt1l.dtsi"
16 phy-handle = <&phy0>;
21 phy0: ethernet-phy@0 {
22 compatible = "ethernet-phy-id2000.0181";
24 interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>;
25 reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
26 reset-assert-us = <10>;
27 reset-deassert-us = <35>;
[all …]
H A Dstm32mp151a-prtt1s.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
8 #include "stm32mp151a-prtt1l.dtsi"
16 phy-handle = <&phy0>;
20 pinctrl-names = "default", "sleep";
21 pinctrl-0 = <&i2c1_pins_a>;
22 pinctrl-1 = <&i2c1_sleep_pins_a>;
23 clock-frequency = <100000>;
24 /delete-property/dmas;
25 /delete-property/dma-names;
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3568-fastrhino-r68s.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "rk3568-fastrhino-r66s.dtsi"
7 compatible = "lunzn,fastrhino-r68s", "rockchip,rk3568";
15 adc-keys {
16 compatible = "adc-keys";
17 io-channels = <&saradc 0>;
18 io-channel-names = "buttons";
19 keyup-threshold-microvolt = <1800000>;
21 button-recovery {
24 press-threshold-microvolt = <1750>;
[all …]
H A Drk3566-orangepi-3b-v1.1.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include "rk3566-orangepi-3b.dtsi"
9 compatible = "xunlong,orangepi-3b-v1.1", "xunlong,orangepi-3b", "rockchip,rk3566";
13 vccio5-supply = <&vcc_3v3>;
17 phy-handle = <&rgmii_phy1>;
22 rgmii_phy1: ethernet-phy@1 {
23 compatible = "ethernet-phy-ieee802.3-c22";
25 reset-assert-us = <20000>;
26 reset-deassert-us = <50000>;
[all …]
H A Drk3328-orangepi-r1-plus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Based on rk3328-nanopi-r2s.dts, which is:
4 * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
7 /dts-v1/;
9 #include "rk3328-orangepi-r1-plus.dtsi"
13 compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
17 phy-handle = <&rtl8211e>;
18 phy-mode = "rgmii";
24 rtl8211e: ethernet-phy@1 {
26 pinctrl-0 = <&eth_phy_reset_pin>;
[all …]
H A Drk3328-nanopi-r2s-plus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
11 #include "rk3328-nanopi-r2s.dtsi"
14 compatible = "friendlyarm,nanopi-r2s-plus", "rockchip,rk3328";
23 bus-width = <8>;
24 cap-mmc-highspeed;
25 disable-wp;
26 mmc-hs200-1_8v;
27 non-removable;
28 pinctrl-names = "default";
[all …]
H A Drk3328-orangepi-r1-plus-lts.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
9 /dts-v1/;
11 #include "rk3328-orangepi-r1-plus.dtsi"
15 compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
19 phy-handle = <&yt8531c>;
20 phy-mode = "rgmii-id";
24 yt8531c: ethernet-phy@0 {
25 compatible = "ethernet-phy-ieee802.3-c22";
28 motorcomm,auto-sleep-disabled;
[all …]
H A Drk3566-radxa-zero-3e.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include "rk3566-radxa-zero-3.dtsi"
9 compatible = "radxa,zero-3e", "rockchip,rk3566";
18 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
19 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
21 phy-handle = <&rgmii_phy1>;
22 phy-mode = "rgmii-id";
23 phy-supply = <&vcc_3v3>;
24 pinctrl-names = "default";
[all …]
H A Drk3588-ok3588-c.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
4 #include "rk3588-fet3588-c.dtsi"
7 model = "Forlinx OK3588-C Board";
8 compatible = "forlinx,ok3588-c", "forlinx,fet3588-c", "rockchip,rk3588";
16 adc-keys-0 {
17 compatible = "adc-keys";
18 io-channels = <&saradc 0>;
19 io-channel-names = "buttons";
20 keyup-threshold-microvolt = <1800000>;
[all …]
H A Drk3566-orangepi-3b-v2.1.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include "rk3566-orangepi-3b.dtsi"
9 compatible = "xunlong,orangepi-3b-v2.1", "xunlong,orangepi-3b", "rockchip,rk3566";
11 vccio_phy1: regulator-1v8-vccio-phy {
12 compatible = "regulator-fixed";
13 regulator-name = "vccio_phy1";
14 regulator-always-on;
15 regulator-boot-on;
16 regulator-max-microvolt = <1800000>;
[all …]
/linux/drivers/reset/
H A Dreset-imx7.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * i.MX7 System Reset Controller (SRC) driver
14 #include <linux/reset-controller.h>
16 #include <dt-bindings/reset/imx7-reset.h>
17 #include <dt-bindings/reset/imx8mq-reset.h>
18 #include <dt-bindings/reset/imx8mp-reset.h>
51 const struct imx7_src_signal *signal = &imx7src->signals[id]; in imx7_reset_update()
53 return regmap_update_bits(imx7src->regmap, in imx7_reset_update()
54 signal->offset, signal->bit, value); in imx7_reset_update()
92 unsigned long id, bool assert) in imx7_reset_set() argument
[all …]
H A Dreset-k230.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2022-2024 Canaan Bright Sight Co., Ltd
4 * Copyright (C) 2024-2025 Junhui Liu <junhui.liu@pigmoral.tech>
6 * The reset management module in the K230 SoC provides reset time control
8 * during which reset is applied or removed while the clock is stopped can be
10 * up to 255 * 0.25 = 63.75 µs. For RST_TYPE_FLUSH, the reset bit is
13 * Although this driver does not configure the reset time registers, delays have
14 * been added to the assert, deassert, and reset operations to cover the maximum
15 * reset time. Some reset types include done bits whose toggle does not
16 * unambiguously signal whether hardware reset removal or clock-stop period
[all …]
/linux/drivers/clk/qcom/
H A Dreset.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/reset-controller.h>
12 #include "reset.h"
18 rcdev->ops->assert(rcdev, id); in qcom_reset()
19 fsleep(rst->reset_map[id].udelay ?: 1); /* use 1 us as default */ in qcom_reset()
21 rcdev->ops->deassert(rcdev, id); in qcom_reset()
26 unsigned long id, bool assert) in qcom_reset_set_assert() argument
33 map = &rst->reset_map[id]; in qcom_reset_set_assert()
34 mask = map->bitmask ? map->bitmask : BIT(map->bit); in qcom_reset_set_assert()
36 regmap_update_bits(rst->regmap, map->reg, mask, assert ? mask : 0); in qcom_reset_set_assert()
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qp-prtwd3.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
16 stdout-path = &uart4;
29 clock_ksz8081: clock-ksz8081 {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <50000000>;
35 clock_ksz9031: clock-ksz9031 {
36 compatible = "fixed-clock";
[all …]
H A Dimx6ull-engicam-microgea.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
12 compatible = "engicam,microgea-imx6ull", "fsl,imx6ull";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_phy_reset>;
23 phy-mode = "rmii";
24 phy-handle = <&ethphy0>;
25 local-mac-address = [00 00 00 00 00 00];
29 #address-cells = <1>;
30 #size-cells = <0>;
[all …]
H A Dimx6qdl-vicut1-12inch.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
7 gpio-keys {
8 compatible = "gpio-keys";
9 pinctrl-names = "default";
10 pinctrl-0 = <&pinctrl_gpiokeys>;
13 power-button {
17 wakeup-source;
24 power-supply = <&reg_3v3>;
28 remote-endpoint = <&lvds0_out>;
35 pinctrl-names = "default";
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dmdio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
17 bus. These should follow the generic ethernet-phy.yaml document, or
22 pattern: '^mdio(-(bus|external))?(@.+|-([0-9]+))?$'
24 "#address-cells":
27 "#size-cells":
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx93-var-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
12 model = "Variscite VAR-SOM-MX93 module";
13 compatible = "variscite,var-som-mx93", "fsl,imx93";
15 mmc_pwrseq: mmc-pwrseq {
16 compatible = "mmc-pwrseq-simple";
17 post-power-on-delay-ms = <100>;
18 power-off-delay-us = <10000>;
19 reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
25 pinctrl-names = "default";
[all …]
H A Dimx8mp-debix-som-a-bmb-08.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "imx8mp-debix-som-a.dtsi"
12 model = "Polyhex i.MX8MPlus Debix SOM A on BMB-08";
13 compatible = "polyhex,imx8mp-debix-som-a-bmb-08", "polyhex,imx8mp-debix-som-a",
22 stdout-path = &uart2;
25 reg_baseboard_vdd3v3: regulator-baseboard-vdd3v3 {
26 compatible = "regulator-fixed";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
[all …]
/linux/fs/xfs/scrub/
H A Drepair.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2018-2023 Oracle. All Rights Reserved.
58 * told us to fix it. This function returns -EAGAIN to mean "re-run scrub",
69 trace_xrep_attempt(XFS_I(file_inode(sc->file)), sc->sm, error); in xrep_attempt()
71 xchk_ag_btcur_free(&sc->sa); in xrep_attempt()
72 xchk_rtgroup_btcur_free(&sc->sr); in xrep_attempt()
75 ASSERT(sc->ops->repair); in xrep_attempt()
76 run->repair_attempted = true; in xrep_attempt()
78 error = sc->ops->repair(sc); in xrep_attempt()
79 trace_xrep_done(XFS_I(file_inode(sc->file)), sc->sm, error); in xrep_attempt()
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxm-gt1-ultimate.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxm.dtsi"
9 #include "meson-gx-p23x-q20x.dtsi"
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
14 compatible = "azw,gt1-ultimate", "amlogic,s912", "amlogic,meson-gxm";
18 compatible = "gpio-leds";
20 led-white {
24 default-state = "on";
[all …]
H A Dmeson-gxm-ugoos-am3.dts1 // SPDX-License-Identifier: GPL-2.0
10 /dts-v1/;
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h>
15 #include "meson-gxm.dtsi"
16 #include "meson-gx-p23x-q20x.dtsi"
19 compatible = "ugoos,am3", "amlogic,s912", "amlogic,meson-gxm";
22 adc-keys {
23 compatible = "adc-keys";
24 io-channels = <&saradc 0>;
[all …]
/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2044-sophgo-srd3-10.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
11 model = "Sophgo SG2044 SRD3-10";
12 compatible = "sophgo,srd3-10", "sophgo,sg2044";
22 stdout-path = "serial1:115200n8";
27 clock-frequency = <25000000>;
31 bus-width = <4>;
32 no-sdio;
33 no-sd;
34 non-removable;
[all …]

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