1*a8281618SDario Binacchi// SPDX-License-Identifier: GPL-2.0 2*a8281618SDario Binacchi/* 3*a8281618SDario Binacchi * Copyright (C) 2025 Amarula Solutions, Dario Binacchi <dario.binacchi@amarulasolutions.com> 4*a8281618SDario Binacchi * Copyright (C) 2025 Engicam srl 5*a8281618SDario Binacchi */ 6*a8281618SDario Binacchi 7*a8281618SDario Binacchi/dts-v1/; 8*a8281618SDario Binacchi 9*a8281618SDario Binacchi #include "imx6ull.dtsi" 10*a8281618SDario Binacchi 11*a8281618SDario Binacchi/ { 12*a8281618SDario Binacchi compatible = "engicam,microgea-imx6ull", "fsl,imx6ull"; 13*a8281618SDario Binacchi 14*a8281618SDario Binacchi memory@80000000 { 15*a8281618SDario Binacchi device_type = "memory"; 16*a8281618SDario Binacchi reg = <0x80000000 0x20000000>; 17*a8281618SDario Binacchi }; 18*a8281618SDario Binacchi}; 19*a8281618SDario Binacchi 20*a8281618SDario Binacchi&fec1 { 21*a8281618SDario Binacchi pinctrl-names = "default"; 22*a8281618SDario Binacchi pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_phy_reset>; 23*a8281618SDario Binacchi phy-mode = "rmii"; 24*a8281618SDario Binacchi phy-handle = <ðphy0>; 25*a8281618SDario Binacchi local-mac-address = [00 00 00 00 00 00]; 26*a8281618SDario Binacchi status = "okay"; 27*a8281618SDario Binacchi 28*a8281618SDario Binacchi mdio { 29*a8281618SDario Binacchi #address-cells = <1>; 30*a8281618SDario Binacchi #size-cells = <0>; 31*a8281618SDario Binacchi 32*a8281618SDario Binacchi ethphy0: ethernet-phy@0 { 33*a8281618SDario Binacchi compatible = "ethernet-phy-ieee802.3-c22"; 34*a8281618SDario Binacchi reg = <0>; 35*a8281618SDario Binacchi reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 36*a8281618SDario Binacchi reset-assert-us = <4000>; 37*a8281618SDario Binacchi reset-deassert-us = <4000>; 38*a8281618SDario Binacchi }; 39*a8281618SDario Binacchi }; 40*a8281618SDario Binacchi}; 41*a8281618SDario Binacchi 42*a8281618SDario Binacchi/* NAND */ 43*a8281618SDario Binacchi&gpmi { 44*a8281618SDario Binacchi pinctrl-names = "default"; 45*a8281618SDario Binacchi pinctrl-0 = <&pinctrl_gpmi_nand>; 46*a8281618SDario Binacchi nand-ecc-mode = "hw"; 47*a8281618SDario Binacchi nand-ecc-strength = <0>; 48*a8281618SDario Binacchi nand-ecc-step-size = <0>; 49*a8281618SDario Binacchi nand-on-flash-bbt; 50*a8281618SDario Binacchi status = "okay"; 51*a8281618SDario Binacchi}; 52*a8281618SDario Binacchi 53*a8281618SDario Binacchi&iomuxc { 54*a8281618SDario Binacchi pinctrl_enet1: enet1grp { 55*a8281618SDario Binacchi fsl,pins = < 56*a8281618SDario Binacchi MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 57*a8281618SDario Binacchi MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 58*a8281618SDario Binacchi MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 59*a8281618SDario Binacchi MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 60*a8281618SDario Binacchi MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 61*a8281618SDario Binacchi MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 62*a8281618SDario Binacchi MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009 63*a8281618SDario Binacchi MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 64*a8281618SDario Binacchi MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 65*a8281618SDario Binacchi >; 66*a8281618SDario Binacchi }; 67*a8281618SDario Binacchi 68*a8281618SDario Binacchi pinctrl_gpmi_nand: gpminandgrp { 69*a8281618SDario Binacchi fsl,pins = < 70*a8281618SDario Binacchi MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 71*a8281618SDario Binacchi MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 72*a8281618SDario Binacchi MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 73*a8281618SDario Binacchi MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 74*a8281618SDario Binacchi MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 75*a8281618SDario Binacchi MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 76*a8281618SDario Binacchi MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 77*a8281618SDario Binacchi MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 78*a8281618SDario Binacchi MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 79*a8281618SDario Binacchi MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 80*a8281618SDario Binacchi MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 81*a8281618SDario Binacchi MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 82*a8281618SDario Binacchi MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 83*a8281618SDario Binacchi MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 84*a8281618SDario Binacchi MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 85*a8281618SDario Binacchi >; 86*a8281618SDario Binacchi }; 87*a8281618SDario Binacchi}; 88*a8281618SDario Binacchi 89*a8281618SDario Binacchi&iomuxc_snvs { 90*a8281618SDario Binacchi pinctrl_phy_reset: phy-resetgrp { 91*a8281618SDario Binacchi fsl,pins = < 92*a8281618SDario Binacchi MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 93*a8281618SDario Binacchi >; 94*a8281618SDario Binacchi }; 95*a8281618SDario Binacchi}; 96