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/linux/Documentation/devicetree/bindings/regulator/
H A Dnvidia,tegra-regulators-coupling.txt4 NVIDIA Tegra SoC's have a mandatory voltage-coupling between regulators.
5 Thus on Tegra20 there are 3 coupled regulators and on NVIDIA Tegra30
9 ------------------------
11 On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU.
16 ------------------------
18 On Tegra30 SoC's there are 2 coupled regulators: CORE and CPU. The CORE
24 - nvidia,tegra-core-regulator: Boolean property that designates regulator
25 as the "Core domain" voltage regulator.
26 - nvidia,tegra-rtc-regulator: Boolean property that designates regulator
27 as the "RTC domain" voltage regulator.
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-evb2-v10.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,vop2.h>
17 compatible = "rockchip,rk3588-evb2-v10", "rockchip,rk3588";
25 stdout-path = "serial2:1500000n8";
28 hdmi-con {
29 compatible = "hdmi-connector";
[all …]
H A Drk3588-evb1-v10.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,vop2.h>
13 #include <dt-bindings/usb/pd.h>
18 compatible = "rockchip,rk3588-evb1-v10", "rockchip,rk3588";
26 stdout-path = "serial2:1500000n8";
29 adc-keys {
[all …]
H A Drk3588s-evb1-v10.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,vop2.h>
13 #include <dt-bindings/usb/pd.h>
18 compatible = "rockchip,rk3588s-evb1-v10", "rockchip,rk3588s";
26 stdout-path = "serial2:1500000n8";
29 adc-keys {
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-nexus7-grouper-ti-pmic.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/interrupt-controller/arm-gic.h>
4 #include <dt-bindings/gpio/gpio.h>
13 #interrupt-cells = <2>;
14 interrupt-controller;
15 wakeup-source;
17 ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>;
18 ti,system-power-controller;
19 ti,sleep-keep-ck32k;
20 ti,sleep-enable;
[all …]
H A Dtegra30-asus-nexus7-grouper-maxim-pmic.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/interrupt-controller/arm-gic.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/mfd/max77620.h>
14 #interrupt-cells = <2>;
15 interrupt-controller;
17 #gpio-cells = <2>;
18 gpio-controller;
20 system-power-controller;
22 pinctrl-names = "default";
[all …]
H A Dtegra20-ventana.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
7 #include "tegra20-cpu-opp.dtsi"
8 #include "tegra20-cpu-opp-microvolt.dtsi"
21 stdout-path = "serial0:115200n8";
40 vdd-supply = <&hdmi_vdd_reg>;
41 pll-supply = <&hdmi_pll_reg>;
43 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
[all …]
H A Dtegra20-paz00.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
8 #include "tegra20-cpu-opp.dtsi"
9 #include "tegra20-cpu-opp-microvolt.dtsi"
25 stdout-path = "serial0:115200n8";
44 vdd-supply = <&hdmi_vdd_reg>;
45 pll-supply = <&hdmi_pll_reg>;
47 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
[all …]
H A Dtegra30-cardhu.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/thermal/thermal.h>
5 #include "tegra30-cpu-opp.dtsi"
6 #include "tegra30-cpu-opp-microvolt.dtsi"
12 * A02 will have different sets of GPIOs for fixed regulator compare to
16 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
17 * tegra30-cardhu-a04.dts.
20 * The sticker will have number like 600-81291-1000-002 C.3. In this 4th
22 * The (downstream internal) U-Boot of Cardhu display the board-id as
[all …]
H A Dtegra20-acer-a500-picasso.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra20-cpu-opp.dtsi"
11 #include "tegra20-cpu-opp-microvolt.dtsi"
32 * pre-existing /chosen node to be available to insert the
41 reserved-memory {
[all …]
H A Dtegra30-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0
15 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
16 nvidia,hpd-gpio =
18 pll-supply = <&reg_1v8_avdd_hdmi_pll>;
19 vdd-supply = <&reg_3v3_avdd_hdmi>;
24 lan-reset-n-hog {
25 gpio-hog;
27 output-high;
28 line-name = "LAN_RESET#";
33 pinctrl-names = "default";
[all …]
H A Dtegra30-asus-transformer-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/input/gpio-keys.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
8 #include "tegra30-cpu-opp.dtsi"
9 #include "tegra30-cpu-opp-microvolt.dtsi"
12 chassis-type = "convertible";
31 * pre-existing /chosen node to be available to insert the
37 trusted-foundations {
38 compatible = "tlm,trusted-foundations";
[all …]
H A Dtegra30-lg-x3.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/input/gpio-keys.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/leds/common.h>
6 #include <dt-bindings/mfd/max77620.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-cpu-opp.dtsi"
11 #include "tegra30-cpu-opp-microvolt.dtsi"
14 chassis-type = "handset";
30 * pre-existing /chosen node to be available to insert the
[all …]
H A Dtegra30-asus-p1801-t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-opp.dtsi"
10 #include "tegra30-cpu-opp-microvolt.dtsi"
13 model = "Asus Portable AiO P1801-T";
14 compatible = "asus,p1801-t", "nvidia,tegra30";
15 chassis-type = "convertible";
[all …]
H A Dtegra30-beaver.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "tegra30-cpu-opp.dtsi"
6 #include "tegra30-cpu-opp-microvolt.dtsi"
19 stdout-path = "serial0:115200n8";
29 avdd-pexa-supply = <&ldo1_reg>;
30 vdd-pexa-supply = <&ldo1_reg>;
31 avdd-pexb-supply = <&ldo1_reg>;
32 vdd-pexb-supply = <&ldo1_reg>;
33 avdd-pex-pll-supply = <&ldo1_reg>;
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dsamsung,s2mps11.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
18 sub-blocks.
23 - samsung,s2mpg10-pmic
24 - samsung,s2mps11-pmic
25 - samsung,s2mps13-pmic
26 - samsung,s2mps14-pmic
27 - samsung,s2mps15-pmic
[all …]
H A Dmaxim,max77802.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Javier Martinez Canillas <javier@dowhile0.org>
11 - Krzysztof Kozlowski <krzk@kernel.org>
18 current regulators (10 high efficiency Buck regulators and 32 Low-DropOut
23 in dt-bindings/clock/maxim,max77802.h.
29 '#clock-cells':
39 $ref: /schemas/regulator/maxim,max77802.yaml
43 inb1-supply:
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8183-evb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
14 chassis-type = "embedded";
15 compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
27 stdout-path = "serial0:921600n8";
30 reserved-memory {
31 #address-cells = <2>;
32 #size-cells = <2>;
35 compatible = "shared-dma-pool";
37 no-map;
[all …]
H A Dmt8192-asurada.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/spmi/spmi.h>
25 stdout-path = "serial0:115200n8";
33 backlight_lcd0: backlight-lcd0 {
34 compatible = "pwm-backlight";
36 power-supply = <&ppvar_sys>;
37 enable-gpios = <&pio 152 0>;
38 brightness-levels = <0 1023>;
[all …]
H A Dmt8390-genio-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Author: Chris Chen <chris-qj.chen@mediatek.com>
9 * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
18 #include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
19 #include <dt-bindings/spmi/spmi.h>
20 #include <dt-bindings/usb/pd.h>
[all …]
H A Dmt8186-corsola.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 /dts-v1/;
7 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/input/gpio-keys.h>
11 #include <dt-bindings/regulator/mediatek,mt6397-regulator.h>
26 stdout-path = "serial0:115200n8";
35 backlight_lcd0: backlight-lcd0 {
36 compatible = "pwm-backlight";
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroid-core.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
14 #include "exynos5422-cpus.dtsi"
27 stdout-path = "serial2:115200n8";
31 compatible = "samsung,secure-firmware";
35 fixed-rate-clocks {
[all …]
H A Dexynos5800-peach-pi.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/clock/maxim,max77802.h>
13 #include <dt-bindings/regulator/maxim,max77802.h>
14 #include <dt-bindings/sound/samsung-i2s.h>
16 #include "exynos5420-cpus.dtsi"
21 compatible = "google,pi-rev16",
[all …]
/linux/drivers/soc/tegra/
H A Dregulators-tegra30.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2019 GRATE-DRIVER project
7 * Copyright (C) 2010-2011 NVIDIA Corporation
10 #define pr_fmt(fmt) "tegra voltage-coupler: " fmt
16 #include <linux/regulator/coupler.h>
17 #include <linux/regulator/driver.h>
18 #include <linux/regulator/machine.h>
52 * Tegra30 SoC has critical DVFS-capable devices that are in tegra30_core_limit()
53 * permanently-active or active at a boot time, like EMC in tegra30_core_limit()
59 * the state of all DVFS-critical CORE devices is synced. in tegra30_core_limit()
[all …]
H A Dregulators-tegra20.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2019 GRATE-DRIVER project
7 * Copyright (C) 2010-2011 NVIDIA Corporation
10 #define pr_fmt(fmt) "tegra voltage-coupler: " fmt
16 #include <linux/regulator/coupler.h>
17 #include <linux/regulator/driver.h>
18 #include <linux/regulator/machine.h>
53 * Tegra20 SoC has critical DVFS-capable devices that are in tegra20_core_limit()
54 * permanently-active or active at a boot time, like EMC in tegra20_core_limit()
60 * the state of all DVFS-critical CORE devices is synced. in tegra20_core_limit()
[all …]

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