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/freebsd/sys/arm64/broadcom/brcmmdio/
H A Dmdio_mux_iproc.c95 struct resource * reg_base; member
161 bus_write_4(sc->reg_base, MDIO_PARAM_OFFSET, param); in brcm_iproc_switch()
173 val = bus_read_4(sc->reg_base, MDIO_STAT_OFFSET); in iproc_mdio_wait_for_idle()
202 bus_write_4(sc->reg_base, MDIO_CTRL_OFFSET, 0); in brcm_iproc_mdio_op()
203 bus_read_4(sc->reg_base, MDIO_STAT_OFFSET); in brcm_iproc_mdio_op()
208 param = bus_read_4(sc->reg_base, MDIO_PARAM_OFFSET); in brcm_iproc_mdio_op()
214 bus_write_4(sc->reg_base, MDIO_PARAM_OFFSET, param); in brcm_iproc_mdio_op()
216 bus_write_4(sc->reg_base, MDIO_ADDR_OFFSET, reg); in brcm_iproc_mdio_op()
218 bus_write_4(sc->reg_base, MDIO_CTRL_OFFSET, op); in brcm_iproc_mdio_op()
225 ret = bus_read_4(sc->reg_base, MDIO_READ_OFFSET) & MDIO_READ_DATA_MASK; in brcm_iproc_mdio_op()
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/freebsd/sys/contrib/dev/athk/ath11k/
H A Dhal.c276 u32 reg_base; in ath11k_hal_srng_dst_hw_init() local
278 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; in ath11k_hal_srng_dst_hw_init()
281 ath11k_hif_write32(ab, reg_base + in ath11k_hal_srng_dst_hw_init()
289 ath11k_hif_write32(ab, reg_base + in ath11k_hal_srng_dst_hw_init()
293 reg_base + HAL_REO1_RING_MSI1_DATA_OFFSET(ab), in ath11k_hal_srng_dst_hw_init()
297 ath11k_hif_write32(ab, reg_base, srng->ring_base_paddr); in ath11k_hal_srng_dst_hw_init()
304 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_BASE_MSB_OFFSET(ab), val); in ath11k_hal_srng_dst_hw_init()
308 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_ID_OFFSET(ab), val); in ath11k_hal_srng_dst_hw_init()
319 reg_base + HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET(ab), in ath11k_hal_srng_dst_hw_init()
325 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_HP_ADDR_LSB_OFFSET(ab), in ath11k_hal_srng_dst_hw_init()
[all …]
/freebsd/sys/contrib/dev/athk/ath12k/
H A Dhal.c1259 u32 reg_base; in ath12k_hal_srng_dst_hw_init() local
1261 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; in ath12k_hal_srng_dst_hw_init()
1264 ath12k_hif_write32(ab, reg_base + in ath12k_hal_srng_dst_hw_init()
1271 ath12k_hif_write32(ab, reg_base + in ath12k_hal_srng_dst_hw_init()
1275 reg_base + ath12k_hal_reo1_ring_msi1_data_offset(ab), in ath12k_hal_srng_dst_hw_init()
1279 ath12k_hif_write32(ab, reg_base, srng->ring_base_paddr); in ath12k_hal_srng_dst_hw_init()
1285 ath12k_hif_write32(ab, reg_base + ath12k_hal_reo1_ring_base_msb_offset(ab), val); in ath12k_hal_srng_dst_hw_init()
1289 ath12k_hif_write32(ab, reg_base + ath12k_hal_reo1_ring_id_offset(ab), val); in ath12k_hal_srng_dst_hw_init()
1299 reg_base + ath12k_hal_reo1_ring_producer_int_setup_offset(ab), in ath12k_hal_srng_dst_hw_init()
1305 ath12k_hif_write32(ab, reg_base + ath12k_hal_reo1_ring_hp_addr_lsb_offset(ab), in ath12k_hal_srng_dst_hw_init()
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Dmac.h990 u32 reg_base, u32 *cr);
1014 u32 rtw89_mac_reg_by_idx(struct rtw89_dev *rtwdev, u32 reg_base, u8 band) in rtw89_mac_txpwr_read32()
1018 return band == 0 ? reg_base : (reg_base + mac->band1_offset); in rtw89_mac_txpwr_read32()
1282 u32 reg_base, u32 *val)
1287 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1296 u32 reg_base, u32 val)
1301 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1310 u32 reg_base, u32 mask, u32 val)
1315 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base,
829 rtw89_mac_reg_by_idx(u32 reg_base,u8 band) rtw89_mac_reg_by_idx() argument
1015 rtw89_mac_txpwr_read32(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 * val) rtw89_mac_txpwr_read32() argument
1028 rtw89_mac_txpwr_write32(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 val) rtw89_mac_txpwr_write32() argument
1041 rtw89_mac_txpwr_write32_mask(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 mask,u32 val) rtw89_mac_txpwr_write32_mask() argument
[all...]
H A Dmac.c4356 u32 reg_base; in rtw89_mac_bcn_fltr_rpt()
4361 reg_base = port >= 4 ? p->bss_color + 4 : p->bss_color; in rtw89_mac_bcn_fltr_rpt()
4362 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif->mac_idx); in rtw89_mac_bcn_fltr_rpt()
5428 u32 reg_base, u32 *cr) in _rtw89_mac_bf_monitor_track()
5431 u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); in _rtw89_mac_bf_monitor_track()
3927 u32 reg_base; rtw89_mac_port_cfg_bss_color() local
4741 rtw89_mac_get_txpwr_cr(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 * cr) rtw89_mac_get_txpwr_cr() argument
/freebsd/sys/dev/vnic/
H A Dthunder_mdio.c142 bus_read_8((sc)->reg_base, (reg))
145 bus_write_8((sc)->reg_base, (reg), (val))
158 sc->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in thunder_mdio_attach()
160 if (sc->reg_base == NULL) { in thunder_mdio_attach()
181 if (sc->reg_base != NULL) { in thunder_mdio_detach()
183 sc->reg_base); in thunder_mdio_detach()
H A Dthunder_bgx.c146 bgx->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in thunder_bgx_attach()
148 if (bgx->reg_base == NULL) { in thunder_bgx_attach()
154 bgx->bgx_id = (rman_get_start(bgx->reg_base) >> BGX_NODE_ID_SHIFT) & in thunder_bgx_attach()
156 bgx->bgx_id += nic_get_node_id(bgx->reg_base) * MAX_BGX_PER_CN88XX; in thunder_bgx_attach()
182 rman_get_rid(bgx->reg_base), bgx->reg_base); in thunder_bgx_attach()
205 rman_get_rid(bgx->reg_base), bgx->reg_base); in thunder_bgx_detach()
220 return (bus_read_8(bgx->reg_base, addr)); in bgx_reg_read()
230 bus_write_8(bgx->reg_base, addr, val); in bgx_reg_write()
240 bus_write_8(bgx->reg_base, addr, val | bus_read_8(bgx->reg_base, addr)); in bgx_reg_modify()
H A Dnicvf_main.c200 nic->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in nicvf_attach()
202 if (nic->reg_base == NULL) { in nicvf_attach()
270 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(nic->reg_base), in nicvf_attach()
271 nic->reg_base); in nicvf_attach()
291 if (nic->reg_base != NULL) { in nicvf_detach()
293 rman_get_rid(nic->reg_base), nic->reg_base); in nicvf_detach()
798 bus_write_8(nic->reg_base, offset, val); in nicvf_reg_write()
805 return (bus_read_8(nic->reg_base, offset)); in nicvf_reg_read()
813 bus_write_8(nic->reg_base, offset + (qidx << NIC_Q_NUM_SHIFT), val); in nicvf_queue_reg_write()
821 return (bus_read_8(nic->reg_base, offset + (qidx << NIC_Q_NUM_SHIFT))); in nicvf_queue_reg_read()
H A Dnic_main.c101 struct resource * reg_base; /* Register start address */ member
208 nic->node = nic_get_node_id(nic->reg_base); in nicpf_attach()
340 nic->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in nicpf_alloc_res()
342 if (nic->reg_base == NULL) { in nicpf_alloc_res()
361 if (nic->reg_base != NULL) { in nicpf_free_res()
363 rman_get_rid(nic->reg_base), nic->reg_base); in nicpf_free_res()
373 bus_write_8(nic->reg_base, offset, val); in nic_reg_write()
381 val = bus_read_8(nic->reg_base, offset); in nic_reg_read()
H A Dthunder_bgx_var.h52 struct resource * reg_base; member
H A Dthunder_mdio_var.h53 struct resource * reg_base; member
H A Dnic.h310 struct resource *reg_base; member
/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dnvidia,tegra124-soctherm.txt106 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
107 0x0 0x60006000 0x0 0x400 /* CAR reg_base */
171 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
172 0x0 0x70040000 0x0 0x200>; /* CCROC reg_base */;
H A Dnvidia,tegra124-soctherm.yaml244 reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */
245 <0x60006000 0x400>; /* CAR reg_base */
310 reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */
311 <0x70040000 0x200>; /* CCROC reg_base */
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Ddma.c667 q->wed_regs = wed->tx_ring[ring].reg_base; in mt76_dma_wed_setup()
678 q->wed_regs = wed->txfree_ring.reg_base; in mt76_dma_wed_setup()
683 q->wed_regs = wed->rx_ring[ring].reg_base; in mt76_dma_wed_setup()
/freebsd/sys/arm64/iommu/
H A Dsmmu.c929 uint64_t reg_base; in smmu_init_strtab_2lvl() local
971 reg_base = base & STRTAB_BASE_ADDR_M; in smmu_init_strtab_2lvl()
972 KASSERT(reg_base == base, ("bad allocation 3")); in smmu_init_strtab_2lvl()
973 reg_base |= STRTAB_BASE_RA; in smmu_init_strtab_2lvl()
974 strtab->base = reg_base; in smmu_init_strtab_2lvl()
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra124.dtsi917 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
918 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra132.dtsi867 reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */
868 <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
H A Dtegra210.dtsi1318 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
1319 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
/freebsd/sys/dev/bnxt/bnxt_en/
H A Dif_bnxt.c1654 u32 reg_base = 0xffffffff; in bnxt_map_fw_health_regs() local
1665 if (reg_base == 0xffffffff) in bnxt_map_fw_health_regs()
1666 reg_base = reg & BNXT_GRC_BASE_MASK; in bnxt_map_fw_health_regs()
1667 if ((reg & BNXT_GRC_BASE_MASK) != reg_base) in bnxt_map_fw_health_regs()
1673 if (reg_base == 0xffffffff) in bnxt_map_fw_health_regs()
1676 __bnxt_map_fw_health_reg(bp, reg_base); in bnxt_map_fw_health_regs()