Lines Matching full:reg_base

276 	u32 reg_base;  in ath11k_hal_srng_dst_hw_init()  local
278 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; in ath11k_hal_srng_dst_hw_init()
281 ath11k_hif_write32(ab, reg_base + in ath11k_hal_srng_dst_hw_init()
289 ath11k_hif_write32(ab, reg_base + in ath11k_hal_srng_dst_hw_init()
293 reg_base + HAL_REO1_RING_MSI1_DATA_OFFSET(ab), in ath11k_hal_srng_dst_hw_init()
297 ath11k_hif_write32(ab, reg_base, srng->ring_base_paddr); in ath11k_hal_srng_dst_hw_init()
304 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_BASE_MSB_OFFSET(ab), val); in ath11k_hal_srng_dst_hw_init()
308 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_ID_OFFSET(ab), val); in ath11k_hal_srng_dst_hw_init()
319 reg_base + HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET(ab), in ath11k_hal_srng_dst_hw_init()
325 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_HP_ADDR_LSB_OFFSET(ab), in ath11k_hal_srng_dst_hw_init()
327 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_HP_ADDR_MSB_OFFSET(ab), in ath11k_hal_srng_dst_hw_init()
331 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2]; in ath11k_hal_srng_dst_hw_init()
332 ath11k_hif_write32(ab, reg_base, 0); in ath11k_hal_srng_dst_hw_init()
333 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_TP_OFFSET(ab), 0); in ath11k_hal_srng_dst_hw_init()
336 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; in ath11k_hal_srng_dst_hw_init()
346 ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_MISC_OFFSET(ab), val); in ath11k_hal_srng_dst_hw_init()
355 u32 reg_base; in ath11k_hal_srng_src_hw_init() local
357 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; in ath11k_hal_srng_src_hw_init()
360 ath11k_hif_write32(ab, reg_base + in ath11k_hal_srng_src_hw_init()
368 ath11k_hif_write32(ab, reg_base + in ath11k_hal_srng_src_hw_init()
372 ath11k_hif_write32(ab, reg_base + in ath11k_hal_srng_src_hw_init()
377 ath11k_hif_write32(ab, reg_base, srng->ring_base_paddr); in ath11k_hal_srng_src_hw_init()
384 ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET(ab), val); in ath11k_hal_srng_src_hw_init()
387 ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_ID_OFFSET(ab), val); in ath11k_hal_srng_src_hw_init()
390 ath11k_hif_write32(ab, reg_base, (u32)srng->ring_base_paddr); in ath11k_hal_srng_src_hw_init()
396 ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET(ab), val); in ath11k_hal_srng_src_hw_init()
411 reg_base + HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(ab), in ath11k_hal_srng_src_hw_init()
420 reg_base + HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(ab), in ath11k_hal_srng_src_hw_init()
428 reg_base + HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(ab), in ath11k_hal_srng_src_hw_init()
431 reg_base + HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(ab), in ath11k_hal_srng_src_hw_init()
436 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2]; in ath11k_hal_srng_src_hw_init()
437 ath11k_hif_write32(ab, reg_base, 0); in ath11k_hal_srng_src_hw_init()
438 ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_TP_OFFSET, 0); in ath11k_hal_srng_src_hw_init()
441 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; in ath11k_hal_srng_src_hw_init()
455 ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_MISC_OFFSET(ab), val); in ath11k_hal_srng_src_hw_init()
967 u32 reg_base; in ath11k_hal_srng_setup() local
1005 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2]; in ath11k_hal_srng_setup()
1022 (u32 *)((unsigned long)ab->mem + reg_base); in ath11k_hal_srng_setup()
1025 "type %d ring_num %d reg_base 0x%x shadow 0x%lx\n", in ath11k_hal_srng_setup()
1027 reg_base, in ath11k_hal_srng_setup()
1055 (u32 *)((unsigned long)ab->mem + reg_base + in ath11k_hal_srng_setup()
1061 reg_base + (HAL_REO1_RING_TP(ab) - in ath11k_hal_srng_setup()