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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_udma_config.c53 uint32_t reg; in al_udma_axi_set() local
57 reg = al_reg_read32(&axi_regs->cfg_2); in al_udma_axi_set()
58 reg &= ~UDMA_GEN_AXI_CFG_2_ARB_PROMOTION_MASK; in al_udma_axi_set()
59 reg |= axi->arb_promotion; in al_udma_axi_set()
60 al_reg_write32(&axi_regs->cfg_2, reg); in al_udma_axi_set()
62 reg = al_reg_read32(&axi_regs->endian_cfg); in al_udma_axi_set()
64 reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_64B_EN; in al_udma_axi_set()
66 reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_64B_EN; in al_udma_axi_set()
69 reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DATA; in al_udma_axi_set()
71 reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DATA; in al_udma_axi_set()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/aspeed/
H A Daspeed-bmc-ibm-fuji.dts175 reg = <0x80000000 0x40000000>;
184 reg = <0xb3d00000 0x100000>;
190 reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */
200 reg = <0xb4000000 0x04000000>; /* 64M */
207 reg = <0xbf000000 0x01000000>; /* 16M */
330 reg = <0x51>;
335 reg = <0x62>;
361 reg = <0x63>;
400 reg = <0x54>;
405 reg = <0x68>;
[all …]
H A Daspeed-bmc-ibm-everest.dts175 reg = <0x80000000 0x40000000>;
185 reg = <0xb3d00000 0x100000>;
190 reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */
201 reg = <0xb4000000 0x04000000>; /* 64M */
208 reg = <0xbf000000 0x01000000>; /* 16M */
327 reg = <0x51>;
332 reg = <0x62>;
359 reg = <0x63>;
398 reg = <0x54>;
403 reg = <0x68>;
[all …]
H A Daspeed-bmc-facebook-santabarbara.dts116 reg = <0x80000000 0x80000000>;
142 reg = <0>;
243 reg = <0x53>;
248 reg = <0x68>;
257 reg = <0x20>;
275 reg = <0x21>;
280 reg = <0x22>;
298 reg = <0x24>;
316 reg = <0x26>;
337 reg = <0x3c>;
[all …]
H A Daspeed-bmc-facebook-cmm.dts335 reg = <0x77>;
342 reg = <0>;
348 reg = <0x70>;
354 reg = <0>;
359 reg = <1>;
364 reg = <2>;
369 reg = <3>;
374 reg = <4>;
379 reg = <5>;
384 reg
[all...]
H A Daspeed-bmc-ibm-rainier.dts40 reg = <0x80000000 0x40000000>;
50 reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */
61 reg = <0xb4000000 0x04000000>; /* 64M */
68 reg = <0xbf000000 0x01000000>; /* 16M */
86 reg = <0>;
92 reg = <1>;
98 reg = <2>;
104 reg = <3>;
263 reg = <0x51>;
268 reg = <0x20>;
[all …]
H A Daspeed-bmc-facebook-fuji-data64.dts213 <0>, /* device reg=<1> does not exist */
221 reg = <2>;
247 reg = <0x70>;
253 reg = <0>;
257 reg = <0x10>;
265 reg = <1>;
271 reg = <2>;
277 reg = <3>;
283 reg = <4>;
289 reg = <5>;
[all …]
H A Daspeed-bmc-facebook-yosemite4.dts49 reg = <0x80000000 0x80000000>;
58 reg = <0xb8dfa000 0x6000>;
86 reg = <0>;
191 reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
196 reg = <0x21>;
203 reg = <0x22>;
215 reg = <0x23>;
222 reg = <0x24>;
229 reg = <0x40>;
242 reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
[all …]
H A Daspeed-bmc-opp-swift.dts17 reg = <0x80000000 0x20000000>;
27 reg = <0x98000000 0x04000000>; /* 64M */
235 reg = < 0 0x60000 >;
239 reg = < 0x60000 0x20000 >;
243 reg = < 0x80000 0x7F80000>;
259 reg = < 0 0x60000 >;
263 reg = < 0x60000 0x20000 >;
267 reg = < 0x80000 0x7F80000>;
342 reg = <0x52>;
348 reg = <0>;
[all …]
H A Daspeed-bmc-ibm-blueridge.dts40 reg = <0x80000000 0x40000000>;
49 reg = <0xb3d00000 0x100000>;
55 reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */
65 reg = <0xb4000000 0x04000000>; /* 64M */
72 reg = <0xbf000000 0x01000000>; /* 16M */
87 reg = <0>;
93 reg = <1>;
99 reg = <2>;
105 reg = <3>;
269 reg = <0x51>;
[all …]
H A Dibm-power10-quad.dtsi9 reg = <0x20>;
14 reg = <0 0>;
21 reg = <0x1000 0x400>;
26 reg = <0x2400 0x400>;
37 reg = <0x20>;
42 reg = <0 0>;
49 reg = <0x1000 0x400>;
54 reg = <0x2400 0x400>;
65 reg = <0x20>;
70 reg = <0 0>;
[all …]
H A Daspeed-bmc-opp-tacoma.dts21 reg = <0x80000000 0x40000000>;
31 reg = <0xb8000000 0x4000000>; /* 64M */
36 reg = <0xbc000000 0x180000>; /* 16 * (3 * 0x8000) */
46 reg = <0xbf000000 0x01000000>; /* 16M */
200 reg = <0 0>;
207 reg = <0x1000 0x400>;
212 reg = <0x1800 0x400>;
217 reg = <0>;
221 reg = <1>;
225 reg = <2>;
[all …]
H A Dibm-power11-dual.dtsi76 reg = <0 0>;
83 reg = <0x1000 0x400>;
88 reg = <0x1800 0x400>;
93 reg = <0>; /* OMI01 */
99 reg = <0x20>;
104 reg = <0 0>;
111 reg = <0x1000 0x400>;
116 reg = <0x2400 0x400>;
123 reg = <1>; /* OMI23 */
129 reg = <0x20>;
[all …]
H A Dibm-power11-quad.dtsi72 reg = <2 0>;
79 reg = <0x1000 0x400>;
84 reg = <0x1800 0x400>;
89 reg = <0>; /* OM01 */
95 reg = <0x20>;
100 reg = <0 0>;
107 reg = <0x1000 0x400>;
112 reg = <0x2400 0x400>;
119 reg = <1>; /* OM23 */
125 reg = <0x20>;
[all …]
/freebsd/sys/dev/qcom_tlmm/
H A Dqcom_tlmm_ipq4018_hw.c71 uint32_t reg; in qcom_tlmm_ipq4018_hw_pin_set_function() local
78 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin, in qcom_tlmm_ipq4018_hw_pin_set_function()
80 reg &= ~(QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_MASK in qcom_tlmm_ipq4018_hw_pin_set_function()
82 reg |= (function & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_MASK) in qcom_tlmm_ipq4018_hw_pin_set_function()
85 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg); in qcom_tlmm_ipq4018_hw_pin_set_function()
99 uint32_t reg; in qcom_tlmm_ipq4018_hw_pin_get_function() local
107 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin, in qcom_tlmm_ipq4018_hw_pin_get_function()
109 reg = reg >> QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_SHIFT; in qcom_tlmm_ipq4018_hw_pin_get_function()
110 reg &= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_MASK; in qcom_tlmm_ipq4018_hw_pin_get_function()
111 *function = reg; in qcom_tlmm_ipq4018_hw_pin_get_function()
[all …]
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c415 uint32_t reg; in pll_enable() local
417 RD4(sc, sc->base_reg, &reg); in pll_enable()
419 reg &= ~PLL_BASE_BYPASS; in pll_enable()
420 reg |= PLL_BASE_ENABLE; in pll_enable()
421 WR4(sc, sc->base_reg, reg); in pll_enable()
428 uint32_t reg; in pll_disable() local
430 RD4(sc, sc->base_reg, &reg); in pll_disable()
432 reg |= PLL_BASE_BYPASS; in pll_disable()
433 reg &= ~PLL_BASE_ENABLE; in pll_disable()
434 WR4(sc, sc->base_reg, reg); in pll_disable()
[all …]
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_xusbpadctl.c459 bus_size_t reg; member
476 .reg = r, \
545 uint32_t reg; in uphy_pex_enable() local
570 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in uphy_pex_enable()
571 reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(~0); in uphy_pex_enable()
572 reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(0x136); in uphy_pex_enable()
573 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg); in uphy_pex_enable()
575 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in uphy_pex_enable()
576 reg &= ~UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(~0); in uphy_pex_enable()
577 reg |= UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(0x2a); in uphy_pex_enable()
[all …]
H A Dtegra210_clk_pll.c600 uint32_t reg; in pll_enable() local
603 RD4(sc, sc->base_reg, &reg); in pll_enable()
605 reg &= ~PLL_BASE_BYPASS; in pll_enable()
606 reg |= PLL_BASE_ENABLE; in pll_enable()
607 WR4(sc, sc->base_reg, reg); in pll_enable()
614 uint32_t reg; in pll_disable() local
616 RD4(sc, sc->base_reg, &reg); in pll_disable()
618 reg |= PLL_BASE_BYPASS; in pll_disable()
619 reg &= ~PLL_BASE_ENABLE; in pll_disable()
620 WR4(sc, sc->base_reg, reg); in pll_disable()
[all …]
/freebsd/usr.sbin/bhyve/gdb/
H A Daarch64-core.xml11 <reg name="x0" bitsize="64"/>
12 <reg name="x1" bitsize="64"/>
13 <reg name="x2" bitsize="64"/>
14 <reg name="x3" bitsize="64"/>
15 <reg name="x4" bitsize="64"/>
16 <reg name="x5" bitsize="64"/>
17 <reg name="x6" bitsize="64"/>
18 <reg name="x7" bitsize="64"/>
19 <reg name="x8" bitsize="64"/>
20 <reg name="x9" bitsize="64"/>
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra194-p3509-0000.dtsi23 reg = <0>;
31 reg = <1>;
49 reg = <0>;
57 reg = <1>;
75 reg = <0>;
84 reg = <1>;
102 reg = <0>;
110 reg = <1>;
127 reg = <0>;
135 reg = <1>;
[all …]
H A Dtegra186-p2771-0000.dts27 reg = <0>;
35 reg = <1>;
53 reg = <0>;
61 reg = <1>;
79 reg = <0>;
87 reg = <1>;
105 reg = <0>;
113 reg = <1>;
131 reg = <0>;
139 reg = <1>;
[all …]
H A Dtegra194-p2972-0000.dts28 reg = <0>;
36 reg = <1>;
54 reg = <0>;
62 reg = <1>;
80 reg = <0>;
88 reg = <1>;
106 reg = <0>;
114 reg = <1>;
132 reg = <0>;
140 reg = <1>;
[all …]
H A Dtegra210-p2371-2180.dts42 reg = <0>;
55 reg = <0x2c>;
82 reg = <0x57>;
138 reg = <0>;
146 reg = <1>;
164 reg = <0>;
172 reg = <1>;
190 reg = <0>;
198 reg = <1>;
216 reg = <0>;
[all …]
/freebsd/sys/arm/freescale/imx/
H A Dimx6_ccm.c91 uint32_t reg; in ccm_init_gates() local
94 reg = CCGR0_AIPS_TZ1 | CCGR0_AIPS_TZ2 | CCGR0_ABPHDMA; in ccm_init_gates()
95 WR4(sc, CCM_CCGR0, reg); in ccm_init_gates()
98 reg = CCGR1_ENET | CCGR1_EPIT1 | CCGR1_GPT | CCGR1_ECSPI1 | in ccm_init_gates()
100 WR4(sc, CCM_CCGR1, reg); in ccm_init_gates()
103 reg = CCGR2_I2C1 | CCGR2_I2C2 | CCGR2_I2C3 | CCGR2_IIM | in ccm_init_gates()
107 WR4(sc, CCM_CCGR2, reg); in ccm_init_gates()
110 reg = CCGR3_OCRAM | CCGR3_MMDC_CORE_IPG | in ccm_init_gates()
112 WR4(sc, CCM_CCGR3, reg); in ccm_init_gates()
115 reg = CCGR4_PL301_MX6QFAST1_S133 | in ccm_init_gates()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/microchip/
H A Dsparx5_pcb135_board.dtsi144 reg = <0>; /* CS0 */
148 reg = <0x9>; /* SPI */
179 reg = <0x0>;
184 reg = <0x1>;
189 reg = <0x2>;
194 reg = <0x3>;
203 reg = <0>;
206 reg = <1>;
209 reg = <2>;
212 reg = <3>;
[all …]

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