Lines Matching full:reg
53 uint32_t reg; in al_udma_axi_set() local
57 reg = al_reg_read32(&axi_regs->cfg_2); in al_udma_axi_set()
58 reg &= ~UDMA_GEN_AXI_CFG_2_ARB_PROMOTION_MASK; in al_udma_axi_set()
59 reg |= axi->arb_promotion; in al_udma_axi_set()
60 al_reg_write32(&axi_regs->cfg_2, reg); in al_udma_axi_set()
62 reg = al_reg_read32(&axi_regs->endian_cfg); in al_udma_axi_set()
64 reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_64B_EN; in al_udma_axi_set()
66 reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_64B_EN; in al_udma_axi_set()
69 reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DATA; in al_udma_axi_set()
71 reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DATA; in al_udma_axi_set()
74 reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DESC; in al_udma_axi_set()
76 reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DESC; in al_udma_axi_set()
79 reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DATA; in al_udma_axi_set()
81 reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DATA; in al_udma_axi_set()
84 reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DESC; in al_udma_axi_set()
86 reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DESC; in al_udma_axi_set()
88 al_reg_write32(&axi_regs->endian_cfg, reg); in al_udma_axi_set()
98 uint32_t reg; in al_udma_m2s_axi_sm_set() local
99 reg = al_reg_read32(cfg_1); in al_udma_m2s_axi_sm_set()
100 reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_1_AWID_MASK; in al_udma_m2s_axi_sm_set()
101 reg |= m2s_sm->id & UDMA_AXI_M2S_COMP_WR_CFG_1_AWID_MASK; in al_udma_m2s_axi_sm_set()
102 reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_1_AWCACHE_MASK; in al_udma_m2s_axi_sm_set()
103 reg |= (m2s_sm->cache_type << in al_udma_m2s_axi_sm_set()
106 reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_1_AWBURST_MASK; in al_udma_m2s_axi_sm_set()
107 reg |= (m2s_sm->burst << UDMA_AXI_M2S_COMP_WR_CFG_1_AWBURST_SHIFT) & in al_udma_m2s_axi_sm_set()
109 al_reg_write32(cfg_1, reg); in al_udma_m2s_axi_sm_set()
111 reg = al_reg_read32(cfg_2); in al_udma_m2s_axi_sm_set()
112 reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_2_AWUSER_MASK; in al_udma_m2s_axi_sm_set()
113 reg |= m2s_sm->used_ext & UDMA_AXI_M2S_COMP_WR_CFG_2_AWUSER_MASK; in al_udma_m2s_axi_sm_set()
114 reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_2_AWSIZE_MASK; in al_udma_m2s_axi_sm_set()
115 reg |= (m2s_sm->bus_size << in al_udma_m2s_axi_sm_set()
118 reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_2_AWQOS_MASK; in al_udma_m2s_axi_sm_set()
119 reg |= (m2s_sm->qos << UDMA_AXI_M2S_COMP_WR_CFG_2_AWQOS_SHIFT) & in al_udma_m2s_axi_sm_set()
121 reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_2_AWPROT_MASK; in al_udma_m2s_axi_sm_set()
122 reg |= (m2s_sm->prot << UDMA_AXI_M2S_COMP_WR_CFG_2_AWPROT_SHIFT) & in al_udma_m2s_axi_sm_set()
124 al_reg_write32(cfg_2, reg); in al_udma_m2s_axi_sm_set()
126 reg = al_reg_read32(cfg_max_beats); in al_udma_m2s_axi_sm_set()
127 reg &= ~UDMA_AXI_M2S_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK; in al_udma_m2s_axi_sm_set()
128 reg |= m2s_sm->max_beats & in al_udma_m2s_axi_sm_set()
130 al_reg_write32(cfg_max_beats, reg); in al_udma_m2s_axi_sm_set()
139 uint32_t reg; in al_udma_m2s_axi_set() local
156 reg = al_reg_read32(&udma->udma_regs->m2s.axi_m2s.data_rd_cfg); in al_udma_m2s_axi_set()
158 reg |= UDMA_AXI_M2S_DATA_RD_CFG_ALWAYS_BREAK_ON_MAX_BOUDRY; in al_udma_m2s_axi_set()
160 reg &= ~UDMA_AXI_M2S_DATA_RD_CFG_ALWAYS_BREAK_ON_MAX_BOUDRY; in al_udma_m2s_axi_set()
161 al_reg_write32(&udma->udma_regs->m2s.axi_m2s.data_rd_cfg, reg); in al_udma_m2s_axi_set()
163 reg = al_reg_read32(&udma->udma_regs->m2s.axi_m2s.desc_wr_cfg_1); in al_udma_m2s_axi_set()
164 reg &= ~UDMA_AXI_M2S_DESC_WR_CFG_1_MIN_AXI_BEATS_MASK; in al_udma_m2s_axi_set()
165 reg |= (axi_m2s->min_axi_beats << in al_udma_m2s_axi_set()
168 al_reg_write32(&udma->udma_regs->m2s.axi_m2s.desc_wr_cfg_1, reg); in al_udma_m2s_axi_set()
170 reg = al_reg_read32(&udma->udma_regs->m2s.axi_m2s.ostand_cfg); in al_udma_m2s_axi_set()
171 reg &= ~UDMA_AXI_M2S_OSTAND_CFG_MAX_DATA_RD_MASK; in al_udma_m2s_axi_set()
172 reg |= axi_m2s->ostand_max_data_read & in al_udma_m2s_axi_set()
174 reg &= ~UDMA_AXI_M2S_OSTAND_CFG_MAX_DESC_RD_MASK; in al_udma_m2s_axi_set()
175 reg |= (axi_m2s->ostand_max_desc_read << in al_udma_m2s_axi_set()
178 reg &= ~UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_REQ_MASK; in al_udma_m2s_axi_set()
179 reg |= (axi_m2s->ostand_max_comp_req << in al_udma_m2s_axi_set()
182 reg &= ~UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_DATA_WR_MASK; in al_udma_m2s_axi_set()
183 reg |= (axi_m2s->ostand_max_comp_write << in al_udma_m2s_axi_set()
186 al_reg_write32(&udma->udma_regs->m2s.axi_m2s.ostand_cfg, reg); in al_udma_m2s_axi_set()
195 uint32_t reg; in al_udma_s2m_axi_sm_set() local
196 reg = al_reg_read32(cfg_1); in al_udma_s2m_axi_sm_set()
197 reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_1_AWID_MASK; in al_udma_s2m_axi_sm_set()
198 reg |= s2m_sm->id & UDMA_AXI_S2M_COMP_WR_CFG_1_AWID_MASK; in al_udma_s2m_axi_sm_set()
199 reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_1_AWCACHE_MASK; in al_udma_s2m_axi_sm_set()
200 reg |= (s2m_sm->cache_type << in al_udma_s2m_axi_sm_set()
203 reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_1_AWBURST_MASK; in al_udma_s2m_axi_sm_set()
204 reg |= (s2m_sm->burst << UDMA_AXI_S2M_COMP_WR_CFG_1_AWBURST_SHIFT) & in al_udma_s2m_axi_sm_set()
206 al_reg_write32(cfg_1, reg); in al_udma_s2m_axi_sm_set()
208 reg = al_reg_read32(cfg_2); in al_udma_s2m_axi_sm_set()
209 reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_2_AWUSER_MASK; in al_udma_s2m_axi_sm_set()
210 reg |= s2m_sm->used_ext & UDMA_AXI_S2M_COMP_WR_CFG_2_AWUSER_MASK; in al_udma_s2m_axi_sm_set()
211 reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_2_AWSIZE_MASK; in al_udma_s2m_axi_sm_set()
212 reg |= (s2m_sm->bus_size << UDMA_AXI_S2M_COMP_WR_CFG_2_AWSIZE_SHIFT) & in al_udma_s2m_axi_sm_set()
214 reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_2_AWQOS_MASK; in al_udma_s2m_axi_sm_set()
215 reg |= (s2m_sm->qos << UDMA_AXI_S2M_COMP_WR_CFG_2_AWQOS_SHIFT) & in al_udma_s2m_axi_sm_set()
217 reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_2_AWPROT_MASK; in al_udma_s2m_axi_sm_set()
218 reg |= (s2m_sm->prot << UDMA_AXI_S2M_COMP_WR_CFG_2_AWPROT_SHIFT) & in al_udma_s2m_axi_sm_set()
220 al_reg_write32(cfg_2, reg); in al_udma_s2m_axi_sm_set()
222 reg = al_reg_read32(cfg_max_beats); in al_udma_s2m_axi_sm_set()
223 reg &= ~UDMA_AXI_S2M_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK; in al_udma_s2m_axi_sm_set()
224 reg |= s2m_sm->max_beats & in al_udma_s2m_axi_sm_set()
226 al_reg_write32(cfg_max_beats, reg); in al_udma_s2m_axi_sm_set()
236 uint32_t reg; in al_udma_s2m_axi_set() local
253 reg = al_reg_read32(&udma->udma_regs->s2m.axi_s2m.desc_rd_cfg_3); in al_udma_s2m_axi_set()
255 reg |= UDMA_AXI_S2M_DESC_RD_CFG_3_ALWAYS_BREAK_ON_MAX_BOUDRY; in al_udma_s2m_axi_set()
257 reg &= ~UDMA_AXI_S2M_DESC_RD_CFG_3_ALWAYS_BREAK_ON_MAX_BOUDRY; in al_udma_s2m_axi_set()
258 al_reg_write32(&udma->udma_regs->s2m.axi_s2m.desc_rd_cfg_3, reg); in al_udma_s2m_axi_set()
260 reg = al_reg_read32(&udma->udma_regs->s2m.axi_s2m.desc_wr_cfg_1); in al_udma_s2m_axi_set()
261 reg &= ~UDMA_AXI_S2M_DESC_WR_CFG_1_MIN_AXI_BEATS_MASK; in al_udma_s2m_axi_set()
262 reg |= (axi_s2m->min_axi_beats << in al_udma_s2m_axi_set()
265 al_reg_write32(&udma->udma_regs->s2m.axi_s2m.desc_wr_cfg_1, reg); in al_udma_s2m_axi_set()
267 reg = al_reg_read32(&udma->udma_regs->s2m.axi_s2m.ostand_cfg_rd); in al_udma_s2m_axi_set()
268 reg &= ~UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_DESC_RD_OSTAND_MASK; in al_udma_s2m_axi_set()
269 reg |= axi_s2m->ostand_max_desc_read & in al_udma_s2m_axi_set()
272 reg &= ~UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_STREAM_ACK_MASK; in al_udma_s2m_axi_set()
273 reg |= (axi_s2m->ack_fifo_depth << in al_udma_s2m_axi_set()
277 al_reg_write32(&udma->udma_regs->s2m.axi_s2m.ostand_cfg_rd, reg); in al_udma_s2m_axi_set()
279 reg = al_reg_read32(&udma->udma_regs->s2m.axi_s2m.ostand_cfg_wr); in al_udma_s2m_axi_set()
280 reg &= ~UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_WR_OSTAND_MASK; in al_udma_s2m_axi_set()
281 reg |= axi_s2m->ostand_max_data_req & in al_udma_s2m_axi_set()
283 reg &= ~UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_BEATS_WR_OSTAND_MASK; in al_udma_s2m_axi_set()
284 reg |= (axi_s2m->ostand_max_data_write << in al_udma_s2m_axi_set()
287 reg &= ~UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_REQ_MASK; in al_udma_s2m_axi_set()
288 reg |= (axi_s2m->ostand_max_comp_req << in al_udma_s2m_axi_set()
291 reg &= ~UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_DATA_WR_OSTAND_MASK; in al_udma_s2m_axi_set()
292 reg |= (axi_s2m->ostand_max_comp_write << in al_udma_s2m_axi_set()
295 al_reg_write32(&udma->udma_regs->s2m.axi_s2m.ostand_cfg_wr, reg); in al_udma_s2m_axi_set()
303 uint32_t reg = al_reg_read32(&udma->udma_regs->m2s.m2s.cfg_len); in al_udma_m2s_packet_size_cfg_set() local
318 reg &= ~UDMA_M2S_CFG_LEN_ENCODE_64K; in al_udma_m2s_packet_size_cfg_set()
320 reg |= UDMA_M2S_CFG_LEN_ENCODE_64K; in al_udma_m2s_packet_size_cfg_set()
322 reg &= ~UDMA_M2S_CFG_LEN_ENCODE_64K; in al_udma_m2s_packet_size_cfg_set()
324 reg &= ~UDMA_M2S_CFG_LEN_MAX_PKT_SIZE_MASK; in al_udma_m2s_packet_size_cfg_set()
325 reg |= conf->max_pkt_size; in al_udma_m2s_packet_size_cfg_set()
327 al_reg_write32(&udma->udma_regs->m2s.m2s.cfg_len, reg); in al_udma_m2s_packet_size_cfg_set()
347 uint32_t reg; in al_udma_m2s_pref_set() local
349 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_1); in al_udma_m2s_pref_set()
350 reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_1_FIFO_DEPTH_MASK; in al_udma_m2s_pref_set()
351 reg |= conf->desc_fifo_depth; in al_udma_m2s_pref_set()
352 al_reg_write32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_1, reg); in al_udma_m2s_pref_set()
354 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_2); in al_udma_m2s_pref_set()
357 reg |= UDMA_M2S_RD_DESC_PREF_CFG_2_PREF_FORCE_RR; in al_udma_m2s_pref_set()
359 reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_2_PREF_FORCE_RR; in al_udma_m2s_pref_set()
365 reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_MASK; in al_udma_m2s_pref_set()
366 reg |= conf->max_desc_per_packet & in al_udma_m2s_pref_set()
368 al_reg_write32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_2, reg); in al_udma_m2s_pref_set()
370 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_3); in al_udma_m2s_pref_set()
371 reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK; in al_udma_m2s_pref_set()
372 reg |= conf->min_burst_below_thr & in al_udma_m2s_pref_set()
375 reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK; in al_udma_m2s_pref_set()
376 reg |=(conf->min_burst_above_thr << in al_udma_m2s_pref_set()
380 reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_MASK; in al_udma_m2s_pref_set()
381 reg |= (conf->pref_thr << in al_udma_m2s_pref_set()
385 al_reg_write32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_3, reg); in al_udma_m2s_pref_set()
387 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.data_cfg); in al_udma_m2s_pref_set()
388 reg &= ~UDMA_M2S_RD_DATA_CFG_DATA_FIFO_DEPTH_MASK; in al_udma_m2s_pref_set()
389 reg |= conf->data_fifo_depth & in al_udma_m2s_pref_set()
392 reg &= ~UDMA_M2S_RD_DATA_CFG_MAX_PKT_LIMIT_MASK; in al_udma_m2s_pref_set()
393 reg |= (conf->max_pkt_limit in al_udma_m2s_pref_set()
396 al_reg_write32(&udma->udma_regs->m2s.m2s_rd.data_cfg, reg); in al_udma_m2s_pref_set()
405 uint32_t reg; in al_udma_m2s_pref_get() local
407 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_1); in al_udma_m2s_pref_get()
409 AL_REG_FIELD_GET(reg, UDMA_M2S_RD_DESC_PREF_CFG_1_FIFO_DEPTH_MASK, in al_udma_m2s_pref_get()
412 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_2); in al_udma_m2s_pref_get()
413 if (reg & UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_MASK) in al_udma_m2s_pref_get()
418 AL_REG_FIELD_GET(reg, in al_udma_m2s_pref_get()
422 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_3); in al_udma_m2s_pref_get()
425 AL_REG_FIELD_GET(reg, in al_udma_m2s_pref_get()
430 AL_REG_FIELD_GET(reg, in al_udma_m2s_pref_get()
434 conf->pref_thr = AL_REG_FIELD_GET(reg, in al_udma_m2s_pref_get()
516 uint32_t reg; in al_udma_s2m_pref_set() local
518 reg = al_reg_read32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_1); in al_udma_s2m_pref_set()
519 reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_1_FIFO_DEPTH_MASK; in al_udma_s2m_pref_set()
520 reg |= conf->desc_fifo_depth; in al_udma_s2m_pref_set()
521 al_reg_write32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_1, reg); in al_udma_s2m_pref_set()
523 reg = al_reg_read32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_2); in al_udma_s2m_pref_set()
526 reg |= UDMA_S2M_RD_DESC_PREF_CFG_2_PREF_FORCE_RR; in al_udma_s2m_pref_set()
528 reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_2_PREF_FORCE_RR; in al_udma_s2m_pref_set()
535 reg |= UDMA_S2M_RD_DESC_PREF_CFG_2_Q_PROMOTION; in al_udma_s2m_pref_set()
537 reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_2_Q_PROMOTION; in al_udma_s2m_pref_set()
540 reg |= UDMA_S2M_RD_DESC_PREF_CFG_2_FORCE_PROMOTION; in al_udma_s2m_pref_set()
542 reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_2_FORCE_PROMOTION; in al_udma_s2m_pref_set()
545 reg |= UDMA_S2M_RD_DESC_PREF_CFG_2_EN_PREF_PREDICTION; in al_udma_s2m_pref_set()
547 reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_2_EN_PREF_PREDICTION; in al_udma_s2m_pref_set()
549 reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_2_PROMOTION_TH_MASK; in al_udma_s2m_pref_set()
550 reg |= (conf->promotion_th in al_udma_s2m_pref_set()
554 al_reg_write32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_2, reg); in al_udma_s2m_pref_set()
556 reg = al_reg_read32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_3); in al_udma_s2m_pref_set()
557 reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_3_PREF_THR_MASK; in al_udma_s2m_pref_set()
558 reg |= (conf->pref_thr << UDMA_S2M_RD_DESC_PREF_CFG_3_PREF_THR_SHIFT) & in al_udma_s2m_pref_set()
561 reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK; in al_udma_s2m_pref_set()
562 reg |= conf->min_burst_below_thr & in al_udma_s2m_pref_set()
565 reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK; in al_udma_s2m_pref_set()
566 reg |=(conf->min_burst_above_thr << in al_udma_s2m_pref_set()
570 al_reg_write32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_3, reg); in al_udma_s2m_pref_set()
572 reg = al_reg_read32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_4); in al_udma_s2m_pref_set()
573 reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_4_A_FULL_THR_MASK; in al_udma_s2m_pref_set()
574 reg |= conf->a_full_thr & UDMA_S2M_RD_DESC_PREF_CFG_4_A_FULL_THR_MASK; in al_udma_s2m_pref_set()
575 al_reg_write32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_4, reg); in al_udma_s2m_pref_set()
585 uint32_t reg; in al_udma_s2m_data_write_set() local
587 reg = al_reg_read32(&udma->udma_regs->s2m.s2m_wr.data_cfg_1); in al_udma_s2m_data_write_set()
588 reg &= ~UDMA_S2M_WR_DATA_CFG_1_DATA_FIFO_DEPTH_MASK; in al_udma_s2m_data_write_set()
589 reg |= conf->data_fifo_depth & in al_udma_s2m_data_write_set()
591 reg &= ~UDMA_S2M_WR_DATA_CFG_1_MAX_PKT_LIMIT_MASK; in al_udma_s2m_data_write_set()
592 reg |= (conf->max_pkt_limit << in al_udma_s2m_data_write_set()
595 reg &= ~UDMA_S2M_WR_DATA_CFG_1_FIFO_MARGIN_MASK; in al_udma_s2m_data_write_set()
596 reg |= (conf->fifo_margin << in al_udma_s2m_data_write_set()
599 al_reg_write32(&udma->udma_regs->s2m.s2m_wr.data_cfg_1, reg); in al_udma_s2m_data_write_set()
601 reg = al_reg_read32(&udma->udma_regs->s2m.s2m_wr.data_cfg_2); in al_udma_s2m_data_write_set()
602 reg &= ~UDMA_S2M_WR_DATA_CFG_2_DESC_WAIT_TIMER_MASK; in al_udma_s2m_data_write_set()
603 reg |= conf->desc_wait_timer & in al_udma_s2m_data_write_set()
605 reg &= ~(UDMA_S2M_WR_DATA_CFG_2_DROP_IF_NO_DESC | in al_udma_s2m_data_write_set()
610 reg |= conf->flags & in al_udma_s2m_data_write_set()
616 al_reg_write32(&udma->udma_regs->s2m.s2m_wr.data_cfg_2, reg); in al_udma_s2m_data_write_set()
625 uint32_t reg = al_reg_read32(&udma->udma_regs->s2m.s2m_comp.cfg_1c); in al_udma_s2m_completion_set() local
626 reg &= ~UDMA_S2M_COMP_CFG_1C_DESC_SIZE_MASK; in al_udma_s2m_completion_set()
627 reg |= conf->desc_size & UDMA_S2M_COMP_CFG_1C_DESC_SIZE_MASK; in al_udma_s2m_completion_set()
629 reg |= UDMA_S2M_COMP_CFG_1C_CNT_WORDS; in al_udma_s2m_completion_set()
631 reg &= ~UDMA_S2M_COMP_CFG_1C_CNT_WORDS; in al_udma_s2m_completion_set()
633 reg |= UDMA_S2M_COMP_CFG_1C_Q_PROMOTION; in al_udma_s2m_completion_set()
635 reg &= ~UDMA_S2M_COMP_CFG_1C_Q_PROMOTION; in al_udma_s2m_completion_set()
637 reg |= UDMA_S2M_COMP_CFG_1C_FORCE_RR; in al_udma_s2m_completion_set()
639 reg &= ~UDMA_S2M_COMP_CFG_1C_FORCE_RR; in al_udma_s2m_completion_set()
640 reg &= ~UDMA_S2M_COMP_CFG_1C_Q_FREE_MIN_MASK; in al_udma_s2m_completion_set()
641 reg |= (conf->q_free_min << UDMA_S2M_COMP_CFG_1C_Q_FREE_MIN_SHIFT) & in al_udma_s2m_completion_set()
643 al_reg_write32(&udma->udma_regs->s2m.s2m_comp.cfg_1c, reg); in al_udma_s2m_completion_set()
645 reg = al_reg_read32(&udma->udma_regs->s2m.s2m_comp.cfg_2c); in al_udma_s2m_completion_set()
646 reg &= ~UDMA_S2M_COMP_CFG_2C_COMP_FIFO_DEPTH_MASK; in al_udma_s2m_completion_set()
647 reg |= conf->comp_fifo_depth in al_udma_s2m_completion_set()
649 reg &= ~UDMA_S2M_COMP_CFG_2C_UNACK_FIFO_DEPTH_MASK; in al_udma_s2m_completion_set()
650 reg |= (conf->unack_fifo_depth in al_udma_s2m_completion_set()
653 al_reg_write32(&udma->udma_regs->s2m.s2m_comp.cfg_2c, reg); in al_udma_s2m_completion_set()
664 uint32_t reg = al_reg_read32(&udma->udma_regs->m2s.m2s_dwrr.cfg_sched); in al_udma_m2s_sc_set() local
667 reg |= UDMA_M2S_DWRR_CFG_SCHED_EN_DWRR; in al_udma_m2s_sc_set()
669 reg &= ~UDMA_M2S_DWRR_CFG_SCHED_EN_DWRR; in al_udma_m2s_sc_set()
672 reg |= UDMA_M2S_DWRR_CFG_SCHED_PKT_MODE_EN; in al_udma_m2s_sc_set()
674 reg &= ~UDMA_M2S_DWRR_CFG_SCHED_PKT_MODE_EN; in al_udma_m2s_sc_set()
676 reg &= ~UDMA_M2S_DWRR_CFG_SCHED_WEIGHT_INC_MASK; in al_udma_m2s_sc_set()
677 reg |= sched->weight << UDMA_M2S_DWRR_CFG_SCHED_WEIGHT_INC_SHIFT; in al_udma_m2s_sc_set()
678 reg &= ~UDMA_M2S_DWRR_CFG_SCHED_INC_FACTOR_MASK; in al_udma_m2s_sc_set()
679 reg |= sched->inc_factor << UDMA_M2S_DWRR_CFG_SCHED_INC_FACTOR_SHIFT; in al_udma_m2s_sc_set()
680 al_reg_write32(&udma->udma_regs->m2s.m2s_dwrr.cfg_sched, reg); in al_udma_m2s_sc_set()
682 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_dwrr.ctrl_deficit_cnt); in al_udma_m2s_sc_set()
683 reg &= ~UDMA_M2S_DWRR_CTRL_DEFICIT_CNT_INIT_MASK; in al_udma_m2s_sc_set()
684 reg |= sched->deficit_init_val; in al_udma_m2s_sc_set()
685 al_reg_write32(&udma->udma_regs->m2s.m2s_dwrr.ctrl_deficit_cnt, reg); in al_udma_m2s_sc_set()
694 uint32_t reg = al_reg_read32( in al_udma_m2s_rlimit_set() local
698 reg |= UDMA_M2S_RATE_LIMITER_GEN_CFG_PKT_MODE_EN; in al_udma_m2s_rlimit_set()
700 reg &= ~UDMA_M2S_RATE_LIMITER_GEN_CFG_PKT_MODE_EN; in al_udma_m2s_rlimit_set()
701 reg &= ~UDMA_M2S_RATE_LIMITER_GEN_CFG_SHORT_CYCLE_SIZE_MASK; in al_udma_m2s_rlimit_set()
702 reg |= mode->short_cycle_sz & in al_udma_m2s_rlimit_set()
704 al_reg_write32(&udma->udma_regs->m2s.m2s_rate_limiter.gen_cfg, reg); in al_udma_m2s_rlimit_set()
706 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rate_limiter.ctrl_token); in al_udma_m2s_rlimit_set()
707 reg &= ~UDMA_M2S_RATE_LIMITER_CTRL_TOKEN_RST_MASK; in al_udma_m2s_rlimit_set()
708 reg |= mode->token_init_val & in al_udma_m2s_rlimit_set()
710 al_reg_write32(&udma->udma_regs->m2s.m2s_rate_limiter.ctrl_token, reg); in al_udma_m2s_rlimit_set()
717 uint32_t reg = al_reg_read32( in al_udma_m2s_rlimit_reset() local
719 reg |= UDMA_M2S_RATE_LIMITER_CTRL_CYCLE_CNT_RST; in al_udma_m2s_rlimit_reset()
721 reg); in al_udma_m2s_rlimit_reset()
729 uint32_t reg = al_reg_read32(®s->cfg_1s); in al_udma_common_rlimit_set() local
731 reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_MAX_BURST_SIZE_MASK; in al_udma_common_rlimit_set()
732 reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_EN; in al_udma_common_rlimit_set()
733 reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_PAUSE; in al_udma_common_rlimit_set()
734 reg |= conf->max_burst_sz & in al_udma_common_rlimit_set()
736 al_reg_write32(®s->cfg_1s, reg); in al_udma_common_rlimit_set()
738 reg = al_reg_read32(®s->cfg_cycle); in al_udma_common_rlimit_set()
739 reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_CYCLE_LONG_CYCLE_SIZE_MASK; in al_udma_common_rlimit_set()
740 reg |= conf->long_cycle_sz & in al_udma_common_rlimit_set()
742 al_reg_write32(®s->cfg_cycle, reg); in al_udma_common_rlimit_set()
744 reg = al_reg_read32(®s->cfg_token_size_1); in al_udma_common_rlimit_set()
745 reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_1_LONG_CYCLE_MASK; in al_udma_common_rlimit_set()
746 reg |= conf->long_cycle & in al_udma_common_rlimit_set()
748 al_reg_write32(®s->cfg_token_size_1, reg); in al_udma_common_rlimit_set()
750 reg = al_reg_read32(®s->cfg_token_size_2); in al_udma_common_rlimit_set()
751 reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_2_SHORT_CYCLE_MASK; in al_udma_common_rlimit_set()
752 reg |= conf->short_cycle & in al_udma_common_rlimit_set()
754 al_reg_write32(®s->cfg_token_size_2, reg); in al_udma_common_rlimit_set()
756 reg = al_reg_read32(®s->mask); in al_udma_common_rlimit_set()
757 reg &= ~0xf; /* only bits 0-3 defined */ in al_udma_common_rlimit_set()
758 reg |= conf->mask & 0xf; in al_udma_common_rlimit_set()
759 al_reg_write32(®s->mask, reg); in al_udma_common_rlimit_set()
767 uint32_t reg; in al_udma_common_rlimit_act() local
771 reg = al_reg_read32(®s->cfg_1s); in al_udma_common_rlimit_act()
772 reg |= UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_EN; in al_udma_common_rlimit_act()
773 al_reg_write32(®s->cfg_1s, reg); in al_udma_common_rlimit_act()
776 reg = al_reg_read32(®s->cfg_1s); in al_udma_common_rlimit_act()
777 reg |= UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_PAUSE; in al_udma_common_rlimit_act()
778 al_reg_write32(®s->cfg_1s, reg); in al_udma_common_rlimit_act()
781 reg = al_reg_read32(®s->sw_ctrl); in al_udma_common_rlimit_act()
782 reg |= UDMA_M2S_STREAM_RATE_LIMITER_SW_CTRL_RST_TOKEN_CNT; in al_udma_common_rlimit_act()
783 al_reg_write32(®s->sw_ctrl, reg); in al_udma_common_rlimit_act()
842 uint32_t reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_cfg_1); in al_udma_m2s_q_sc_set() local
844 reg &= ~UDMA_M2S_Q_DWRR_CFG_1_MAX_DEFICIT_CNT_SIZE_MASK; in al_udma_m2s_q_sc_set()
845 reg |= conf->max_deficit_cnt_sz & in al_udma_m2s_q_sc_set()
848 reg |= UDMA_M2S_Q_DWRR_CFG_1_STRICT; in al_udma_m2s_q_sc_set()
850 reg &= ~UDMA_M2S_Q_DWRR_CFG_1_STRICT; in al_udma_m2s_q_sc_set()
851 al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_cfg_1, reg); in al_udma_m2s_q_sc_set()
853 reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_cfg_2); in al_udma_m2s_q_sc_set()
854 reg &= ~UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_MASK; in al_udma_m2s_q_sc_set()
855 reg |= (conf->axi_qos << UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_SHIFT) & in al_udma_m2s_q_sc_set()
857 reg &= ~UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_MASK; in al_udma_m2s_q_sc_set()
858 reg |= conf->q_qos & UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_MASK; in al_udma_m2s_q_sc_set()
859 al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_cfg_2, reg); in al_udma_m2s_q_sc_set()
861 reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_cfg_3); in al_udma_m2s_q_sc_set()
862 reg &= ~UDMA_M2S_Q_DWRR_CFG_3_WEIGHT_MASK; in al_udma_m2s_q_sc_set()
863 reg |= conf->weight & UDMA_M2S_Q_DWRR_CFG_3_WEIGHT_MASK; in al_udma_m2s_q_sc_set()
864 al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_cfg_3, reg); in al_udma_m2s_q_sc_set()
871 uint32_t reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_cfg_1); in al_udma_m2s_q_sc_pause() local
874 reg |= UDMA_M2S_Q_DWRR_CFG_1_PAUSE; in al_udma_m2s_q_sc_pause()
876 reg &= ~UDMA_M2S_Q_DWRR_CFG_1_PAUSE; in al_udma_m2s_q_sc_pause()
877 al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_cfg_1, reg); in al_udma_m2s_q_sc_pause()
884 uint32_t reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_sw_ctrl); in al_udma_m2s_q_sc_reset() local
886 reg |= UDMA_M2S_Q_DWRR_SW_CTRL_RST_CNT; in al_udma_m2s_q_sc_reset()
887 al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_sw_ctrl, reg); in al_udma_m2s_q_sc_reset()
896 uint32_t reg = al_reg_read32(&udma->udma_regs->m2s.m2s_comp.cfg_1c); in al_udma_m2s_comp_timeouts_set() local
899 reg |= UDMA_M2S_COMP_CFG_1C_FORCE_RR; in al_udma_m2s_comp_timeouts_set()
901 reg &= ~UDMA_M2S_COMP_CFG_1C_FORCE_RR; in al_udma_m2s_comp_timeouts_set()
909 reg |= UDMA_M2S_COMP_CFG_1C_Q_PROMOTION; in al_udma_m2s_comp_timeouts_set()
911 reg &= ~UDMA_M2S_COMP_CFG_1C_Q_PROMOTION; in al_udma_m2s_comp_timeouts_set()
912 reg &= ~UDMA_M2S_COMP_CFG_1C_COMP_FIFO_DEPTH_MASK; in al_udma_m2s_comp_timeouts_set()
913 reg |= in al_udma_m2s_comp_timeouts_set()
916 reg &= ~UDMA_M2S_COMP_CFG_1C_UNACK_FIFO_DEPTH_MASK; in al_udma_m2s_comp_timeouts_set()
917 reg |= conf->unack_fifo_depth in al_udma_m2s_comp_timeouts_set()
919 al_reg_write32(&udma->udma_regs->m2s.m2s_comp.cfg_1c, reg); in al_udma_m2s_comp_timeouts_set()
924 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_comp.cfg_application_ack); in al_udma_m2s_comp_timeouts_set()
925 reg &= ~UDMA_M2S_COMP_CFG_APPLICATION_ACK_TOUT_MASK; in al_udma_m2s_comp_timeouts_set()
926 reg |= conf->app_timeout << UDMA_M2S_COMP_CFG_APPLICATION_ACK_TOUT_SHIFT; in al_udma_m2s_comp_timeouts_set()
927 al_reg_write32(&udma->udma_regs->m2s.m2s_comp.cfg_application_ack, reg); in al_udma_m2s_comp_timeouts_set()
934 uint32_t reg = al_reg_read32(&udma->udma_regs->m2s.m2s_comp.cfg_1c); in al_udma_m2s_comp_timeouts_get() local
936 if (reg & UDMA_M2S_COMP_CFG_1C_FORCE_RR) in al_udma_m2s_comp_timeouts_get()
941 if (reg & UDMA_M2S_COMP_CFG_1C_Q_PROMOTION) in al_udma_m2s_comp_timeouts_get()
947 AL_REG_FIELD_GET(reg, in al_udma_m2s_comp_timeouts_get()
951 AL_REG_FIELD_GET(reg, in al_udma_m2s_comp_timeouts_get()
958 reg = al_reg_read32( in al_udma_m2s_comp_timeouts_get()
962 AL_REG_FIELD_GET(reg, in al_udma_m2s_comp_timeouts_get()
974 uint32_t reg; in al_udma_s2m_no_desc_cfg_set() local
976 reg = al_reg_read32(&udma->udma_regs->s2m.s2m_wr.data_cfg_2); in al_udma_s2m_no_desc_cfg_set()
984 reg |= UDMA_S2M_WR_DATA_CFG_2_DROP_IF_NO_DESC; in al_udma_s2m_no_desc_cfg_set()
986 reg &= ~UDMA_S2M_WR_DATA_CFG_2_DROP_IF_NO_DESC; in al_udma_s2m_no_desc_cfg_set()
989 reg |= UDMA_S2M_WR_DATA_CFG_2_HINT_IF_NO_DESC; in al_udma_s2m_no_desc_cfg_set()
991 reg &= ~UDMA_S2M_WR_DATA_CFG_2_HINT_IF_NO_DESC; in al_udma_s2m_no_desc_cfg_set()
993 …AL_REG_FIELD_SET(reg, UDMA_S2M_WR_DATA_CFG_2_DESC_WAIT_TIMER_MASK, UDMA_S2M_WR_DATA_CFG_2_DESC_WAI… in al_udma_s2m_no_desc_cfg_set()
995 al_reg_write32(&udma->udma_regs->s2m.s2m_wr.data_cfg_2, reg); in al_udma_s2m_no_desc_cfg_set()
1003 uint32_t reg = al_reg_read32(&udma_q->q_regs->s2m_q.comp_cfg); in al_udma_s2m_q_compl_updade_config() local
1006 reg |= UDMA_S2M_Q_COMP_CFG_EN_COMP_RING_UPDATE; in al_udma_s2m_q_compl_updade_config()
1008 reg &= ~UDMA_S2M_Q_COMP_CFG_EN_COMP_RING_UPDATE; in al_udma_s2m_q_compl_updade_config()
1010 al_reg_write32(&udma_q->q_regs->s2m_q.comp_cfg, reg); in al_udma_s2m_q_compl_updade_config()
1019 uint32_t reg = al_reg_read32(&udma_q->q_regs->s2m_q.comp_cfg); in al_udma_s2m_q_compl_coal_config() local
1022 reg &= ~UDMA_S2M_Q_COMP_CFG_DIS_COMP_COAL; in al_udma_s2m_q_compl_coal_config()
1024 reg |= UDMA_S2M_Q_COMP_CFG_DIS_COMP_COAL; in al_udma_s2m_q_compl_coal_config()
1026 al_reg_write32(&udma_q->q_regs->s2m_q.comp_cfg, reg); in al_udma_s2m_q_compl_coal_config()
1056 uint32_t reg = al_reg_read32(&udma_q->q_regs->s2m_q.pkt_cfg); in al_udma_s2m_q_compl_hdr_split_config() local
1058 reg &= ~UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_MASK; in al_udma_s2m_q_compl_hdr_split_config()
1059 reg &= ~UDMA_S2M_Q_PKT_CFG_EN_HDR_SPLIT; in al_udma_s2m_q_compl_hdr_split_config()
1060 reg &= ~UDMA_S2M_Q_PKT_CFG_FORCE_HDR_SPLIT; in al_udma_s2m_q_compl_hdr_split_config()
1063 reg |= hdr_len & UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_MASK; in al_udma_s2m_q_compl_hdr_split_config()
1064 reg |= UDMA_S2M_Q_PKT_CFG_EN_HDR_SPLIT; in al_udma_s2m_q_compl_hdr_split_config()
1067 reg |= UDMA_S2M_Q_PKT_CFG_FORCE_HDR_SPLIT; in al_udma_s2m_q_compl_hdr_split_config()
1070 al_reg_write32(&udma_q->q_regs->s2m_q.pkt_cfg, reg); in al_udma_s2m_q_compl_hdr_split_config()
1079 uint32_t reg = al_reg_read32(&udma_q->q_regs->s2m_q.comp_cfg); in al_udma_s2m_q_comp_set() local
1081 reg |= UDMA_S2M_Q_COMP_CFG_EN_COMP_RING_UPDATE; in al_udma_s2m_q_comp_set()
1083 reg &= ~UDMA_S2M_Q_COMP_CFG_EN_COMP_RING_UPDATE; in al_udma_s2m_q_comp_set()
1086 reg |= UDMA_S2M_Q_COMP_CFG_DIS_COMP_COAL; in al_udma_s2m_q_comp_set()
1088 reg &= ~UDMA_S2M_Q_COMP_CFG_DIS_COMP_COAL; in al_udma_s2m_q_comp_set()
1090 al_reg_write32(&udma_q->q_regs->s2m_q.comp_cfg, reg); in al_udma_s2m_q_comp_set()
1094 reg = al_reg_read32(&udma_q->q_regs->s2m_q.pkt_cfg); in al_udma_s2m_q_comp_set()
1096 reg &= ~UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_MASK; in al_udma_s2m_q_comp_set()
1097 reg |= conf->hdr_split_size & UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_MASK; in al_udma_s2m_q_comp_set()
1099 reg |= UDMA_S2M_Q_PKT_CFG_FORCE_HDR_SPLIT; in al_udma_s2m_q_comp_set()
1101 reg &= ~UDMA_S2M_Q_PKT_CFG_FORCE_HDR_SPLIT; in al_udma_s2m_q_comp_set()
1103 reg |= UDMA_S2M_Q_PKT_CFG_EN_HDR_SPLIT; in al_udma_s2m_q_comp_set()
1105 reg &= ~UDMA_S2M_Q_PKT_CFG_EN_HDR_SPLIT; in al_udma_s2m_q_comp_set()
1107 al_reg_write32(&udma_q->q_regs->s2m_q.pkt_cfg, reg); in al_udma_s2m_q_comp_set()
1109 reg = al_reg_read32(&udma_q->q_regs->s2m_q.qos_cfg); in al_udma_s2m_q_comp_set()
1110 reg &= ~UDMA_S2M_QOS_CFG_Q_QOS_MASK; in al_udma_s2m_q_comp_set()
1111 reg |= conf->q_qos & UDMA_S2M_QOS_CFG_Q_QOS_MASK; in al_udma_s2m_q_comp_set()
1112 al_reg_write32(&udma_q->q_regs->s2m_q.qos_cfg, reg); in al_udma_s2m_q_comp_set()