91 	uint32_t reg;  in ccm_init_gates()  local
94 	reg = CCGR0_AIPS_TZ1 | CCGR0_AIPS_TZ2 | CCGR0_ABPHDMA;  in ccm_init_gates()
95 	WR4(sc, CCM_CCGR0, reg);  in ccm_init_gates()
98 	reg = CCGR1_ENET | CCGR1_EPIT1 | CCGR1_GPT | CCGR1_ECSPI1 |  in ccm_init_gates()
100 	WR4(sc, CCM_CCGR1, reg);  in ccm_init_gates()
103 	reg = CCGR2_I2C1 | CCGR2_I2C2 | CCGR2_I2C3 | CCGR2_IIM |  in ccm_init_gates()
107 	WR4(sc, CCM_CCGR2, reg);  in ccm_init_gates()
110 	reg = CCGR3_OCRAM | CCGR3_MMDC_CORE_IPG |  in ccm_init_gates()
112 	WR4(sc, CCM_CCGR3, reg);  in ccm_init_gates()
115 	reg = CCGR4_PL301_MX6QFAST1_S133 |  in ccm_init_gates()
117 	WR4(sc, CCM_CCGR4, reg);  in ccm_init_gates()
120 	reg = CCGR5_SDMA | CCGR5_SSI1 | CCGR5_SSI2 | CCGR5_SSI3 |  in ccm_init_gates()
122 	WR4(sc, CCM_CCGR5, reg);  in ccm_init_gates()
125 	reg = CCGR6_USBOH3 | CCGR6_USDHC1 | CCGR6_USDHC2 |  in ccm_init_gates()
127 	WR4(sc, CCM_CCGR6, reg);  in ccm_init_gates()
148 	uint32_t reg;  in ccm_attach()  local
177 	reg = RD4(sc, CCM_CGPR);  in ccm_attach()
178 	reg |= CCM_CGPR_INT_MEM_CLK_LPM;  in ccm_attach()
179 	WR4(sc, CCM_CGPR, reg);  in ccm_attach()
180 	reg = RD4(sc, CCM_CLPCR);  in ccm_attach()
181 	reg = (reg & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM_RUN;  in ccm_attach()
182 	WR4(sc, CCM_CLPCR, reg);  in ccm_attach()
215 	uint32_t reg;  in imx_ccm_ssi_configure()  local
224 	reg = RD4(sc, CCM_CSCMR1);  in imx_ccm_ssi_configure()
225 	reg &= ~(SSI_CLK_SEL_M << SSI1_CLK_SEL_S);  in imx_ccm_ssi_configure()
226 	reg |= (SSI_CLK_SEL_PLL4 << SSI1_CLK_SEL_S);  in imx_ccm_ssi_configure()
227 	reg &= ~(SSI_CLK_SEL_M << SSI2_CLK_SEL_S);  in imx_ccm_ssi_configure()
228 	reg |= (SSI_CLK_SEL_PLL4 << SSI2_CLK_SEL_S);  in imx_ccm_ssi_configure()
229 	reg &= ~(SSI_CLK_SEL_M << SSI3_CLK_SEL_S);  in imx_ccm_ssi_configure()
230 	reg |= (SSI_CLK_SEL_PLL4 << SSI3_CLK_SEL_S);  in imx_ccm_ssi_configure()
231 	WR4(sc, CCM_CSCMR1, reg);  in imx_ccm_ssi_configure()
239 	reg = RD4(sc, CCM_CS1CDR);  in imx_ccm_ssi_configure()
241 	reg &= ~(SSI_CLK_PODF_MASK << SSI1_CLK_PODF_SHIFT);  in imx_ccm_ssi_configure()
242 	reg &= ~(SSI_CLK_PODF_MASK << SSI3_CLK_PODF_SHIFT);  in imx_ccm_ssi_configure()
243 	reg |= (0x1 << SSI1_CLK_PODF_SHIFT);  in imx_ccm_ssi_configure()
244 	reg |= (0x1 << SSI3_CLK_PODF_SHIFT);  in imx_ccm_ssi_configure()
246 	reg &= ~(SSI_CLK_PRED_MASK << SSI1_CLK_PRED_SHIFT);  in imx_ccm_ssi_configure()
247 	reg &= ~(SSI_CLK_PRED_MASK << SSI3_CLK_PRED_SHIFT);  in imx_ccm_ssi_configure()
248 	reg |= (0x3 << SSI1_CLK_PRED_SHIFT);  in imx_ccm_ssi_configure()
249 	reg |= (0x3 << SSI3_CLK_PRED_SHIFT);  in imx_ccm_ssi_configure()
250 	WR4(sc, CCM_CS1CDR, reg);  in imx_ccm_ssi_configure()
253 	reg = RD4(sc, CCM_CS2CDR);  in imx_ccm_ssi_configure()
255 	reg &= ~(SSI_CLK_PODF_MASK << SSI2_CLK_PODF_SHIFT);  in imx_ccm_ssi_configure()
256 	reg |= (0x1 << SSI2_CLK_PODF_SHIFT);  in imx_ccm_ssi_configure()
258 	reg &= ~(SSI_CLK_PRED_MASK << SSI2_CLK_PRED_SHIFT);  in imx_ccm_ssi_configure()
259 	reg |= (0x3 << SSI2_CLK_PRED_SHIFT);  in imx_ccm_ssi_configure()
260 	WR4(sc, CCM_CS2CDR, reg);  in imx_ccm_ssi_configure()
397 	uint32_t reg;  in imx_ccm_pll_video_enable()  local
401 	reg = RD4(ccm_sc, CCM_ANALOG_PLL_VIDEO);  in imx_ccm_pll_video_enable()
402 	reg &= ~CCM_ANALOG_PLL_VIDEO_POWERDOWN;  in imx_ccm_pll_video_enable()
403 	WR4(ccm_sc, CCM_ANALOG_PLL_VIDEO, reg);  in imx_ccm_pll_video_enable()
409 	reg &= ~CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK;  in imx_ccm_pll_video_enable()
410 	reg |= CCM_ANALOG_PLL_VIDEO_POST_DIV_2;  in imx_ccm_pll_video_enable()
411 	reg &= ~CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK;  in imx_ccm_pll_video_enable()
412 	reg |= 37 << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT;  in imx_ccm_pll_video_enable()
413 	WR4(ccm_sc, CCM_ANALOG_PLL_VIDEO, reg);  in imx_ccm_pll_video_enable()
419 	reg = RD4(ccm_sc, CCM_ANALOG_PLL_VIDEO);  in imx_ccm_pll_video_enable()
420 	reg &= ~CCM_ANALOG_PLL_VIDEO_POWERDOWN;  in imx_ccm_pll_video_enable()
421 	WR4(ccm_sc, CCM_ANALOG_PLL_VIDEO, reg);  in imx_ccm_pll_video_enable()
434 	reg |= CCM_ANALOG_PLL_VIDEO_ENABLE;  in imx_ccm_pll_video_enable()
435 	reg &= ~CCM_ANALOG_PLL_VIDEO_BYPASS;  in imx_ccm_pll_video_enable()
436 	WR4(ccm_sc, CCM_ANALOG_PLL_VIDEO, reg);  in imx_ccm_pll_video_enable()
445 	uint32_t reg;  in imx_ccm_ipu_enable()  local
448 	reg = RD4(sc, CCM_CCGR3);  in imx_ccm_ipu_enable()
450 		reg |= CCGR3_IPU1_IPU | CCGR3_IPU1_DI0;  in imx_ccm_ipu_enable()
452 		reg |= CCGR3_IPU2_IPU | CCGR3_IPU2_DI0;  in imx_ccm_ipu_enable()
453 	WR4(sc, CCM_CCGR3, reg);  in imx_ccm_ipu_enable()
456 	reg = RD4(sc, CCM_CHSCCDR);  in imx_ccm_ipu_enable()
457 	reg &= ~(CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |  in imx_ccm_ipu_enable()
459 	reg |= (CHSCCDR_PODF_DIVIDE_BY_3 << CHSCCDR_IPU1_DI0_PODF_SHIFT);  in imx_ccm_ipu_enable()
460 	reg |= (CHSCCDR_IPU_PRE_CLK_PLL5 << CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT);  in imx_ccm_ipu_enable()
461 	WR4(sc, CCM_CHSCCDR, reg);  in imx_ccm_ipu_enable()
463 	reg |= (CHSCCDR_CLK_SEL_PREMUXED << CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT);  in imx_ccm_ipu_enable()
464 	WR4(sc, CCM_CHSCCDR, reg);  in imx_ccm_ipu_enable()
478 	uint32_t reg;  in imx_ccm_hdmi_enable()  local
481 	reg = RD4(sc, CCM_CCGR2);  in imx_ccm_hdmi_enable()
482 	reg |= CCGR2_HDMI_TX | CCGR2_HDMI_TX_ISFR;  in imx_ccm_hdmi_enable()
483 	WR4(sc, CCM_CCGR2, reg);  in imx_ccm_hdmi_enable()