| /freebsd/sys/contrib/device-tree/Bindings/display/ti/ |
| H A D | ti,dra7-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,dra7-dss"
12 - reg: address and length of the register spaces for 'dss'
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
16 - syscon: phandle to control module core syscon node
23 - reg: address and length of the register spaces for 'pll1_clkctrl',
25 - clocks: handle to video1 pll clock and video2 pll clock
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| H A D | ti,omap5-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap5-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, DSI, HDMI
22 - Video port for DPI output
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| H A D | ti,omap4-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap4-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, VENC, DSI, HDMI
22 - Video port for DPI output
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| H A D | ti,omap3-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap3-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - Video ports:
19 - Port 0: DPI output
20 - Port 1: SDI output
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| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | snps,dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
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| H A D | host-generic-pci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
19 Configuration Spaces.
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
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| H A D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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| /freebsd/sys/contrib/device-tree/Bindings/net/can/ |
| H A D | ti_hecc.txt | 8 - compatible: "ti,am3517-hecc"
9 - reg: addresses and lengths of the register spaces for 'hecc', 'hecc-ram'
11 - reg-names :"hecc", "hecc-ram", "mbx"
12 - interrupts: interrupt mapping for the hecc interrupts sources
13 - clocks: clock phandles (see clock bindings for details)
16 - ti,use-hecc1int: if provided configures HECC to produce all interrupts
19 - xceiver-supply: regulator that powers the CAN transceiver
25 compatible = "ti,am3517-hecc";
26 reg = <0x5c050000 0x80>,
29 reg-names = "hecc", "hecc-ram", "mbx";
|
| /freebsd/sys/contrib/device-tree/Bindings/remoteproc/ |
| H A D | ti,omap-remoteproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remotepro
[all...] |
| H A D | mtk,scp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tinghan Shen <tinghan.shen@mediatek.com>
13 This binding provides support for ARM Cortex M4 Co-processor found on some
19 - mediatek,mt8183-scp
20 - mediatek,mt8186-scp
21 - mediatek,mt8188-scp
22 - mediatek,mt8188-scp-dual
23 - mediatek,mt8192-scp
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| H A D | xlnx,zynqmp-r5fss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
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| H A D | ti,k3-r5f-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5
[all...] |
| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | marvell,pxa168.txt | 8 - compatible: should be one of the following.
9 - "marvell,pxa168-clock" - controller compatible with PXA168 SoC.
11 - reg: physical base address of the clock subsystem and length of memory mapped
13 "mpmu", "apmu", "apbc". So three reg spaces need to be defined.
15 - #clock-cells: should be 1.
16 - #reset-cells: should be 1.
21 All these identifier could be found in <dt-bindings/clock/marvell,pxa168.h>.
|
| H A D | marvell,pxa910.txt | 8 - compatible: should be one of the following.
9 - "marvell,pxa910-clock" - controller compatible with PXA910 SoC.
11 - reg: physical base address of the clock subsystem and length of memory mapped
13 "mpmu", "apmu", "apbc", "apbcp". So four reg spaces need to be defined.
15 - #clock-cells: should be 1.
16 - #reset-cells: should be 1.
21 All these identifier could be found in <dt-bindings/clock/marvell-pxa910.h>.
|
| /freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | interlaken-lac.txt | 2 Freescale Interlaken Look-Aside Controller Device Bindings
6 - Interlaken Look-Aside Controller (LAC) Node
7 - Example LAC Node
8 - Interlaken Look-Aside Controller (LAC) Software Portal Node
9 - Interlaken Look-Aside Controller (LAC) Software Portal Child Nodes
10 - Example LAC SWP Node with Child Nodes
13 Interlaken Look-Aside Controller (LAC) Node
17 The Interlaken is a narrow, high speed channelized chip-to-chip interface. To
18 facilitate interoperability between a data path device and a look-aside
19 co-processor, the Interlaken Look-Aside protocol is defined for short
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| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | da8xx-usb.txt | 3 For DA8xx/OMAP-L1x/AM17xx/AM18xx platforms.
7 - compatible : Should be set to "ti,da830-musb".
9 - reg: Offset and length of the USB controller register set.
11 - interrupts: The USB interrupt number.
13 - interrupt-names: Should be set to "mc".
15 - dr_mode: The USB operation mode. Should be one of "host", "peripheral" or "otg".
17 - phys: Phandle for the PHY device
19 - phy-names: Should be "usb-phy"
21 - dmas: specifies the dma channels
23 - dma-names: specifies the names of the channels. Use "rxN" for receive
[all …]
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| H A D | am33xx-usb.txt | 3 - compatible: ti,am33xx-usb
4 - reg: offset and length of the usbss register sets
5 - ti,hwmods : must be "usb_otg_hs"
13 - compatible: ti,am335x-usb-ctrl-module
14 - reg: offset and length of the "USB control registers" in the "Control
17 - reg-names: "phy_ctrl" for the "USB control registers" and "wakeup" for
22 compatible: ti,am335x-usb-phy
23 reg: offset and length of the "USB PHY" register space
25 reg-names: phy
31 - compatible: ti,musb-am33xx
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| /freebsd/sys/dev/bhnd/siba/ |
| H A D | siba_subr.c | 1 /*-
2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
55 * Map a siba(4) OCP vendor code to its corresponding JEDEC JEP-106 vendor
89 for (u_int i = 0; i < nitems(dinfo->cfg); i++) { in siba_alloc_dinfo()
90 dinfo->cfg[i] = ((struct siba_cfg_block){ in siba_alloc_dinfo()
93 .cb_rid = -1, in siba_alloc_dinfo()
95 dinfo->cfg_res[i] = NULL; in siba_alloc_dinfo()
96 dinfo->cfg_rid[i] = -1; in siba_alloc_dinfo()
99 resource_list_init(&dinfo->resources); in siba_alloc_dinfo()
101 dinfo->pmu_state = SIBA_PMU_NONE; in siba_alloc_dinfo()
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| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | nvidia,tegra186-gpio.txt | 42 extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
43 describes the port-level mapping. In that file, the naming convention for ports
52 both the overall controller HW module and the sets-of-ports as "controllers".
56 interrupt signals generated by a set-of-ports. The intent is for each generated
59 per-port-set signals is reported via a separate register. Thus, a driver needs
66 - compatible
69 - "nvidia,tegra186-gpio".
70 - "nvidia,tegra186-gpio-aon".
71 - "nvidia,tegra194-gpio".
72 - "nvidia,tegra194-gpio-aon".
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | brcm,spi-bcm-qspi.txt | 9 io with 3-byte and 4-byte addressing support.
18 - #address-cells:
21 - #size-cells:
24 - compatible:
26 "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on BRCMSTB SoCs
27 "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi" : Second Instance of MSPI
29 "brcm,spi-bcm7425-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
31 "brcm,spi-bcm7429-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
33 "brcm,spi-bcm7435-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
35 "brcm,spi-bcm7445-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/fsi/ |
| H A D | fsi.txt | 4 The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
8 that is an I2C master - the I2C bus can be described by the device tree under
13 the fsi-master-* binding specifications.
18 fsi-master {
19 /* top-level of FSI bus topology, bound to an FSI master driver and
22 fsi-slave@<link,id> {
26 fsi-slave-engine@<addr> {
32 fsi-slave-engine@<addr> {
39 Note that since the bus is probe-able, some (or all) of the topology may
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| /freebsd/sys/dev/liquidio/base/ |
| H A D | lio_device.h | 58 /* Endian-swap modes supported by Octeon. */
74 /*--------------- PCI BAR1 index registers -------------*/
120 /*---------------------------DISPATCH LIST-------------------------------*/
131 /* Singly-linked tail queue node for this entry */
134 /* Singly-linked tail queue head for this entry */
162 /*----------------------- THE OCTEON DEVICE ---------------------------*/
167 * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of
168 * Octeon gets mapped to different physical address spaces in
273 * See octeon-drv-opcodes.h for values.
398 /* This device's id - set by the driver. */
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| /freebsd/sys/arm/mv/armada/ |
| H A D | thermal.c | 1 /*-
62 /* Formula coefficients: temp = (b + m * reg) / div */
137 if (ofw_bus_is_compatible(dev, "marvell,armada380-thermal")) { in armada_thermal_probe()
139 sc->tdata = &armada380_tdata; in armada_thermal_probe()
159 /* Allocate CTRL and STAT register spaces */ in armada_thermal_attach()
161 sc->stat_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, in armada_thermal_attach()
163 if (sc->stat_res == NULL) { in armada_thermal_attach()
170 sc->ctrl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, in armada_thermal_attach()
172 if (sc->ctrl_res == NULL) { in armada_thermal_attach()
176 rman_get_rid(sc->stat_res), sc->stat_res); in armada_thermal_attach()
[all …]
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| /freebsd/crypto/krb5/src/windows/leash/htmlhelp/html/ |
| H A D | Password_Tips.htm | 1 <!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML//EN">
4 <meta name="GENERATOR" content="Microsoft® HTML Help Workshop 4.1">
25 …ds, and misspellings to make it more secure. Remember that you can have spaces in your password. …
|
| /freebsd/sys/contrib/device-tree/Bindings/soc/ti/ |
| H A D | ti,pruss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
23 peripheral interfaces, fast real-time responses, or specialized data handling.
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