Lines Matching +full:reg +full:- +full:spaces
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
26 - $ref: /schemas/pci/pci-ep.yaml#
27 - $ref: /schemas/pci/snps,dw-pcie-common.yaml#
30 reg:
32 DBI, DBI2 reg-spaces and outbound memory window are required for the
34 if the space is unrolled (IP-core version >= 4.80a).
38 reg-names:
43 - description:
44 Basic DWC PCIe controller configuration-space accessible over
47 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
51 - description:
52 Shadow DWC PCIe config-space registers. This space is selected
54 the PCI-SIG PCIe CFG-space with the shadow registers for some
56 mainly relevant for the end-point controller configuration,
60 - description:
61 External Local Bus registers. It's an application-dependent
64 be accessed over some platform-specific means (for instance
67 - description:
71 and CS2 = 1. For IP-core releases prior v4.80a, these registers
77 - description:
78 Platform-specific eDMA registers. Some platforms may have eDMA
79 CSRs mapped in a non-standard base address. The registers offset
80 can be changed or the MS/LS-bits of the address can be attached
81 in an additional RTL block before the MEM-IO transactions reach
84 - description:
89 platform-specific method.
91 - description:
92 Outbound iATU-capable memory-region which will be used to
93 generate various application-specific traffic on the PCIe bus
98 - description:
99 Vendor-specific CSR names. Consider using the generic names above
102 - description: See native 'elbi/app' CSR region for details.
104 - description: See native 'atu' CSR region for details.
107 - contains:
109 - contains:
115 but in addition to the native set the platforms may have a link- or
116 PM-related IRQs specified.
120 interrupt-names:
125 - description:
129 - description:
134 - description:
140 pattern: '^dma([0-9]|1[0-5])?$'
141 - description:
146 - description:
150 - description:
151 Application-specific IRQ raised depending on the vendor-specific
154 - description:
155 Vendor-specific IRQ names. Consider using the generic names above
158 - description: See native "app" IRQ for details
161 max-functions:
165 - compatible
166 - reg
167 - reg-names
172 - |
173 pcie-ep@dfd00000 {
174 compatible = "snps,dw-pcie-ep";
175 reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
178 reg-names = "dbi", "dbi2", "addr_space";
181 interrupt-names = "dma0", "dma1";
184 clock-names = "dbi", "ref";
187 reset-names = "dbi", "phy";
190 phy-names = "pcie0", "pcie1", "pcie2", "pcie3";
192 max-link-speed = <3>;
193 max-functions = /bits/ 8 <4>;