| /freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | dcsr.txt | 17 debug blocks defined within this memory space.
21 - compatible
24 Definition: Must include "fsl,dcsr" and "simple-bus".
25 The DCSR space exists in the memory-mapped bus.
27 - #address-cells
33 - #size-cells
40 - range
[all...] |
| H A D | dma.txt | 4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
13 DMA channels and the address space of the DMA controller
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
[all …]
|
| H A D | interlaken-lac.txt | 2 Freescale Interlaken Look-Aside Controller Device Bindings
6 - Interlaken Look-Aside Controller (LAC) Node
7 - Example LAC Node
8 - Interlaken Look-Aside Controller (LAC) Software Portal Node
9 - Interlaken Look-Aside Controller (LAC) Software Portal Child Nodes
10 - Example LAC SWP Node with Child Nodes
13 Interlaken Look-Aside Controller (LAC) Node
17 The Interlaken is a narrow, high speed channelized chip-to-chip interface. To
18 facilitate interoperability between a data path device and a look-aside
19 co-processor, the Interlaken Look-Aside protocol is defined for short
[all …]
|
| H A D | raideng.txt | 3 RAID Engine nodes are defined to describe on-chip RAID accelerators. Each RAID
11 - compatible: Should contain "fsl,raideng-v1.0" as the value
15 - reg: offset and length of the register set for the device
16 - ranges: standard ranges property specifying the translation
17 between child address space and parent address space
22 compatible = "fsl,raideng-v1.0";
23 #address-cell
[all...] |
| /freebsd/sys/contrib/device-tree/Bindings/mtd/ |
| H A D | st,stm32-fmc2-nand.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/st,stm32-fmc2-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
15 - st,stm32mp15-fmc2
16 - st,stm32mp1-fmc2-nfc
17 - st,stm32mp25-fmc2-nfc
19 reg:
28 - description: tx DMA channel
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | designware-pcie.txt | 4 - compatible:
5 "snps,dw-pcie" for RC mode;
6 "snps,dw-pcie-ep" for EP mode;
7 - reg: For designware cores version < 4.80 contains the configuration
8 address space. For designware core version >= 4.80, contains
9 the configuration and ATU address space
10 - reg-names: Must be "config" for the PCIe configuration space and "atu" for
11 the ATU address space.
12 (The old way of getting the configuration address space from "ranges"
15 - #address-cells: set to <3>
[all …]
|
| H A D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
[all …]
|
| H A D | snps,dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
[all …]
|
| H A D | nvidia,tegra20-pcie.txt | 4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
[all …]
|
| H A D | nvidia,tegra194-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
23 Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
29 - nvidia,tegra194-pcie-ep
[all …]
|
| H A D | nvidia,tegra194-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | altera_tse.txt | 1 * Altera Triple-Speed Ethernet MAC driver (TSE)
4 - compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
5 be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
8 - reg: Address and length of the register set for the device. It contains
9 the information of registers in the same order as described by reg-names
10 - reg-names: Should contain the reg names
11 "control_port": MAC configuration space region
12 "tx_csr": xDMA Tx dispatcher control and status space region
13 "tx_desc": MSGDMA Tx dispatcher descriptor space region
14 "rx_csr" : xDMA Rx dispatcher control and status space region
[all …]
|
| /freebsd/sys/dts/arm/ |
| H A D | annapurna-alpine.dts | 1 /*-
28 /dts-v1/;
32 #address-cells = <1>;
33 #size-cells = <1>;
40 #address-cells = <1>;
41 #size-cells = <0>;
45 compatible = "arm,cortex-a15";
46 reg = <0x0>;
47 d-cache-line-size = <64>; // 64 bytes
48 i-cache-line-size = <64>; // 64 bytes
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/net/pcs/ |
| H A D | snps,dw-xpcs.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/pcs/snps,dw-xpcs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Serge Semin <fancer.lancer@gmail.com>
17 optionally synthesized with a vendor-specific interface connected to
23 right to the system IO memory space.
28 - description: Synopsys DesignWare XPCS with none or unknown PMA
29 const: snps,dw-xpcs
30 - description: Synopsys DesignWare XPCS with Consumer Gen1 3G PMA
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | apm-xgene-dma.txt | 1 Applied Micro X-Gene SoC DMA nodes
3 DMA nodes are defined to describe on-chip DMA interfaces in
4 APM X-Gene SoC.
7 - compatible: Should be "apm,xgene-dma".
8 - device_type: set to "dma".
9 - reg: Address and length of the register set for the device.
11 1st - DMA control and status register address space.
12 2nd - Descriptor ring control and status register address space.
13 3rd - Descriptor ring command register address space.
14 4th - Soc efuse register address space.
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/display/ti/ |
| H A D | ti,omap3-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap3-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - Video ports:
19 - Port 0: DPI output
20 - Port 1: SDI output
[all …]
|
| H A D | ti,omap4-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap4-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, VENC, DSI, HDMI
22 - Video port for DPI output
[all …]
|
| H A D | ti,omap2-dss.txt | 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap2-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
16 - Video port for DPI output
19 - data-lines: number of lines used
23 -----
26 - compatible: "ti,omap2-dispc"
27 - reg: address and length of the register space
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | brcm,dpfe-cpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/brcm,dpfe-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Markus Mayer <mmayer@broadcom.com>
16 - enum:
17 - brcm,bcm7271-dpfe-cpu
18 - brcm,bcm7268-dpfe-cpu
19 - const: brcm,dpfe-cpu
[all …]
|
| H A D | brcm,dpfe-cpu.txt | 8 specified in a single reg property.
11 - compatible: must be "brcm,bcm7271-dpfe-cpu", "brcm,bcm7268-dpfe-cpu"
12 or "brcm,dpfe-cpu"
13 - reg: must reference three register ranges
14 - start address and length of the DCPU register space
15 - start address and length of the DCPU data memory space
16 - start address and length of the DCPU instruction memory space
17 - reg-names: must contain "dpfe-cpu", "dpfe-dmem", and "dpfe-imem";
21 dpfe_cpu0: dpfe-cpu@f1132000 {
22 compatible = "brcm,bcm7271-dpfe-cpu", "brcm,dpfe-cpu";
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/pwm/ |
| H A D | pwm-tipwmss.txt | 4 - compatible: Must be "ti,<soc>-pwmss".
5 for am33xx - compatible = "ti,am33xx-pwmss";
6 for am4372 - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
7 for dra746 - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"
9 - reg: physical base address and size of the registers map.
10 - address-cells: Specify the number of u32 entries needed in child nodes.
12 - size-cells: specify number of u32 entries needed to specify child nodes size
13 in reg property. Should set to 1.
14 - ranges: describes the address mapping of a memory-mapped bus. Should set to
16 parent's address space and length of the address map. For am33xx,
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | ti_qspi.txt | 4 - compatible : should be "ti,dra7xxx-qspi" or "ti,am4372-qspi".
5 - reg: Should contain QSPI registers location and length.
6 - reg-names: Should contain the resource reg names.
7 - qspi_base: Qspi configuration register Address space
8 - qspi_mmap: Memory mapped Address space
9 - (optional) qspi_ctrlmod: Control module Address space
10 - interrupts: should contain the qspi interrupt number.
11 - #address-cells, #size-cells : Must be present if the device has sub-nodes
12 - ti,hwmods: Name of the hwmod associated to the QSPI
15 - spi-max-frequency: Definition as per
[all …]
|
| /freebsd/sys/contrib/device-tree/src/powerpc/ |
| H A D | currituck.dts | 11 /dts-v1/;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 dcr-parent = <&{/cpus/cpu@0}>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 reg = <0>;
34 clock-frequency = <1600000000>; // 1.6 GHz
35 timebase-frequency = <100000000>; // 100Mhz
36 i-cache-line-size = <32>;
[all …]
|
| H A D | akebono.dts | 12 /dts-v1/;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 reg = <0>;
35 clock-frequency = <1600000000>; // 1.6 GHz
36 timebase-frequency = <100000000>; // 100Mhz
37 i-cache-line-size = <32>;
[all …]
|
| /freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
| H A D | fsl-ls2088a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2088A family SoC.
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a72-pmu";
25 compatible = "arm,cortex-a72";
26 reg = <0x0>;
28 cpu-idle-states = <&CPU_PW20>;
29 next-level-cache = <&cluster0_l2>;
30 #cooling-cells = <2>;
[all …]
|