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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap24xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
12 ti,bit-shift = <2>;
13 reg = <0x4>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <6>;
[all …]
H A Domap2430-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <0>;
11 compatible = "ti,composite-mux-clock";
13 reg = <0x78>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <2>;
27 reg = <0x78>;
[all …]
H A Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
23 #clock-cells = <0>;
[all …]
H A Domap2420-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <0>;
11 compatible = "ti,composite-no-wait-gate-clock";
13 ti,bit-shift = <15>;
14 reg = <0x0070>;
18 #clock-cells = <0>;
19 compatible = "ti,composite-mux-clock";
21 ti,bit-shift = <8>;
22 reg = <0x0070>;
26 #clock-cells = <0>;
[all …]
H A Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
21 reg = <0x0108>;
[all …]
H A Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <31>;
14 reg = <0x0040>;
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
[all …]
H A Ddra7xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 atl_clkin0_ck: clock-atl-clkin0 {
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
11 clock-output-names = "atl_clkin0_ck";
15 atl_clkin1_ck: clock-atl-clkin1 {
16 #clock-cells = <0>;
17 compatible = "ti,dra7-atl-clock";
18 clock-output-names = "atl_clkin1_ck";
22 atl_clkin2_ck: clock-atl-clkin2 {
[all …]
H A Dam35xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,am35xx-gate-clock";
12 reg = <0x032c>;
13 ti,bit-shift = <1>;
17 #clock-cells = <0>;
18 compatible = "ti,gate-clock";
20 reg = <0x032c>;
21 ti,bit-shift = <9>;
25 #clock-cells = <0>;
[all …]
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <3>;
17 #clock-cells = <0>;
18 compatible = "fixed-factor-clock";
20 clock-mult = <1>;
21 clock-div = <5>;
26 #clock-cells = <0>;
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_reg_utils.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
53 /* *INDENT-OFF* */
57 /* *INDENT-ON* */
66 #define AL_REG_FIELD_GET(reg, mask, shift) (((reg) & (mask)) >> (shift)) argument
69 #define AL_REG_FIELD_SET(reg, mask, shift, val) \ argument
70 (reg) = \
71 (((reg) & (~(mask))) | \
72 ((((unsigned)(val)) << (shift)) & (mask)))
75 #define AL_REG_FIELD_SET_64(reg, mask, shift, val) \ argument
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Dgate.txt4 quite much similar to the basic gate-clock [2], however,
7 will be controlled instead and the corresponding hw-ops for
10 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
11 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
15 - compatible : shall be one of:
16 "ti,gate-clock" - basic gate clock
17 "ti,wait-gate-clock" - gate clock which waits until clock is active before
19 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
20 "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
21 "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
[all …]
H A Ddivider.txt4 register-mapped adjustable clock rate divider that does not gate and has
15 ti,index-starts-at-one - valid divisor values start at 1, not the default
22 ti,index-power-of-two - valid divisor values are powers of two. E.g:
39 Any zero value in this array means the corresponding bit-value is invalid
44 the number of bits to shift that mask, if necessary. If the shift value
45 is missing it is the same as supplying a zero shift.
50 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
54 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
55 - #clock-cells : from common clock binding; shall be set to 0.
56 - clocks : link to phandle of parent clock
[all …]
H A Dmux.txt4 register-mapped multiplexer with multiple input clock signals or
22 "index-starts-at-one" modified the scheme as follows:
30 the number of bits to shift the control field in the register can be
31 supplied. If the shift value is missing it is the same as supplying
32 a zero shift.
34 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
37 - compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
38 - #clock-cells : from common clock binding; shall be set to 0.
39 - clocks : link phandles of parent clocks
40 - reg : register offset for register controlling adjustable mux
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/nuvoton/
H A Dnuvoton-common-npcm8xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/clock/nuvoton,npcm845-clk.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/interrupt-controlle
[all...]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dkeystone-pll.txt9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - #clock-cells : from common clock binding; shall be set to 0.
13 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
14 - clocks : parent clock phandle
15 - reg - pll control0 and pll multiplier registers
16 - reg-names : control, multiplier and post-divider. The multiplier and
17 post-divider registers are applicable only for main pll clock
18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
23 #clock-cells = <0>;
24 compatible = "ti,keystone,main-pll-clock";
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIProgramInfo.cpp1 //===-- SIProgramInfo.cpp ----------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
80 uint64_t Reg = S_00B848_PRIORITY(ProgInfo.Priority) | in getComputePGMRSrc1Reg() local
88 Reg |= S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp); in getComputePGMRSrc1Reg()
91 Reg |= S_00B848_IEEE_MODE(ProgInfo.IEEEMode); in getComputePGMRSrc1Reg()
94 Reg |= S_00B848_RR_WG_MODE(ProgInfo.RrWgMode); in getComputePGMRSrc1Reg()
96 return Reg; in getComputePGMRSrc1Reg()
101 uint64_t Reg = S_00B848_PRIORITY(ProgInfo.Priority) | in getPGMRSrc1Reg() local
[all …]
/freebsd/sys/arm/freescale/vybrid/
H A Dvf_adc.c1 /*-
28 * Vybrid Family 12-bit Analog to Digital Converter (ADC)
53 #define ADC_HC0 0x00 /* Ctrl reg for hardware triggers */
54 #define ADC_HC1 0x04 /* Ctrl reg for hardware triggers */
57 #define HC_ADCH_S 0 /* Input Channel Select Shift */
61 #define ADC_R0 0x0C /* Data result reg for HW triggers */
62 #define ADC_R1 0x10 /* Data result reg for HW triggers */
66 #define CFG_AVGS_S 14 /* Hardware Average select Shift */
69 #define CFG_REFSEL_S 11 /* Voltage Reference Select Shift */
73 #define CFG_ADLPC (1 << 7) /* Low-Power Configuration */
[all …]
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_super.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
39 #include <dt-bindings/clock/tegra210-car.h>
125 super_mux_get_state(uint32_t reg) in super_mux_get_state() argument
127 reg = (reg >> SUPER_MUX_STATE_BIT_SHIFT) & SUPER_MUX_STATE_BIT_MASK; in super_mux_get_state()
128 if (reg & SUPER_MUX_STATE_BIT_FIQ) in super_mux_get_state()
130 if (reg & SUPER_MUX_STATE_BIT_IRQ) in super_mux_get_state()
132 if (reg & SUPER_MUX_STATE_BIT_RUN) in super_mux_get_state()
134 if (reg & SUPER_MUX_STATE_BIT_IDLE) in super_mux_get_state()
143 uint32_t reg; in super_mux_init() local
[all …]
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_super.c1 /*-
38 #include <dt-bindings/clock/tegra124-car.h>
135 super_mux_get_state(uint32_t reg) in super_mux_get_state() argument
137 reg = (reg >> SUPER_MUX_STATE_BIT_SHIFT) & SUPER_MUX_STATE_BIT_MASK; in super_mux_get_state()
138 if (reg & SUPER_MUX_STATE_BIT_FIQ) in super_mux_get_state()
140 if (reg & SUPER_MUX_STATE_BIT_IRQ) in super_mux_get_state()
142 if (reg & SUPER_MUX_STATE_BIT_RUN) in super_mux_get_state()
144 if (reg & SUPER_MUX_STATE_BIT_IDLE) in super_mux_get_state()
153 uint32_t reg; in super_mux_init() local
154 int shift, state; in super_mux_init() local
[all …]
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Danatop-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/anatop-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
13 - $ref: regulator.yaml#
17 const: fsl,anatop-regulator
19 regulator-name: true
21 anatop-reg-offset:
25 anatop-vol-bit-shift:
[all …]
/freebsd/sys/dev/clk/
H A Dclk_mux.c1 /*-
55 uint32_t shift; member
73 uint32_t reg; in clknode_mux_init() local
80 rv = RD4(clk, sc->offset, &reg); in clknode_mux_init()
85 reg = (reg >> sc->shift) & sc->mask; in clknode_mux_init()
86 clknode_init_parent_idx(clk, reg); in clknode_mux_init()
93 uint32_t reg; in clknode_mux_set_mux() local
100 rv = MD4(clk, sc->offset, sc->mask << sc->shift, in clknode_mux_set_mux()
101 (idx & sc->mask) << sc->shift); in clknode_mux_set_mux()
106 RD4(clk, sc->offset, &reg); in clknode_mux_set_mux()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/intel/
H A Dkeembay-soc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
22 reg = <0x0>;
23 enable-method = "psci";
[all …]
/freebsd/sys/contrib/device-tree/src/mips/netlogic/
H A Dxlp_evp.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 model = "netlogic,XLP-EVP";
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <2>;
15 #size-cells = <1>;
16 compatible = "simple-bus";
23 reg = <0 0x30100 0xa00>;
24 reg-shift = <2>;
[all …]
H A Dxlp_fvp.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 model = "netlogic,XLP-FVP";
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <2>;
15 #size-cells = <1>;
16 compatible = "simple-bus";
23 reg = <0 0x30100 0xa00>;
24 reg-shift = <2>;
[all …]
H A Dxlp_svp.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 model = "netlogic,XLP-SVP";
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <2>;
15 #size-cells = <1>;
16 compatible = "simple-bus";
23 reg = <0 0x30100 0xa00>;
24 reg-shift = <2>;
[all …]

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