1 /*-
38 #include <dt-bindings/clock/tegra124-car.h>
135 super_mux_get_state(uint32_t reg)  in super_mux_get_state()  argument
137 	reg = (reg >> SUPER_MUX_STATE_BIT_SHIFT) & SUPER_MUX_STATE_BIT_MASK;  in super_mux_get_state()
138 	if (reg & SUPER_MUX_STATE_BIT_FIQ)  in super_mux_get_state()
140 	if (reg & SUPER_MUX_STATE_BIT_IRQ)  in super_mux_get_state()
142 	if (reg & SUPER_MUX_STATE_BIT_RUN)  in super_mux_get_state()
144 	if (reg & SUPER_MUX_STATE_BIT_IDLE)  in super_mux_get_state()
153 	uint32_t reg;  in super_mux_init()  local
154 	int shift, state;  in super_mux_init()  local
159 	RD4(sc, sc->base_reg, &reg);  in super_mux_init()
161 	state = super_mux_get_state(reg);  in super_mux_init()
168 	shift = state * SUPER_MUX_MUX_WIDTH;  in super_mux_init()
170 	sc->mux = (reg >> shift) & ((1 << SUPER_MUX_MUX_WIDTH) - 1);  in super_mux_init()
176 	if (sc->flags & SMF_HAVE_DIVIDER_2) {  in super_mux_init()
177 		if (((reg & SUPER_MUX_LP_DIV2_BYPASS) == 0) &&  in super_mux_init()
178 		    (sc->mux == sc->src_pllx))  in super_mux_init()
179 		sc->mux = sc->src_div2;  in super_mux_init()
181 	clknode_init_parent_idx(clk, sc->mux);  in super_mux_init()
191 	int shift, state;  in super_mux_set_mux()  local
192 	uint32_t reg, dummy;  in super_mux_set_mux()  local
197 	RD4(sc, sc->base_reg, &reg);  in super_mux_set_mux()
198 	state = super_mux_get_state(reg);  in super_mux_set_mux()
204 	shift = (state - 1) * SUPER_MUX_MUX_WIDTH;  in super_mux_set_mux()
205 	sc->mux = idx;  in super_mux_set_mux()
206 	if (sc->flags & SMF_HAVE_DIVIDER_2) {  in super_mux_set_mux()
207 		if (idx == sc->src_div2) {  in super_mux_set_mux()
208 			idx = sc->src_pllx;  in super_mux_set_mux()
209 			reg &= ~SUPER_MUX_LP_DIV2_BYPASS;  in super_mux_set_mux()
210 			WR4(sc, sc->base_reg, reg);  in super_mux_set_mux()
211 			RD4(sc, sc->base_reg, &dummy);  in super_mux_set_mux()
212 		} else if (idx == sc->src_pllx) {  in super_mux_set_mux()
213 			reg = SUPER_MUX_LP_DIV2_BYPASS;  in super_mux_set_mux()
214 			WR4(sc, sc->base_reg, reg);  in super_mux_set_mux()
215 			RD4(sc, sc->base_reg, &dummy);  in super_mux_set_mux()
218 	reg &= ~(((1 << SUPER_MUX_MUX_WIDTH) - 1) << shift);  in super_mux_set_mux()
219 	reg |= idx << shift;  in super_mux_set_mux()
221 	WR4(sc, sc->base_reg, reg);  in super_mux_set_mux()
222 	RD4(sc, sc->base_reg, &dummy);  in super_mux_set_mux()
235 	    &clkdef->clkdef);  in super_mux_register()
240 	sc->clkdev = clknode_get_device(clk);  in super_mux_register()
241 	sc->base_reg = clkdef->base_reg;  in super_mux_register()
242 	sc->src_pllx = clkdef->src_pllx;  in super_mux_register()
243 	sc->src_div2 = clkdef->src_div2;  in super_mux_register()
244 	sc->flags = clkdef->flags;  in super_mux_register()
256 		rv = super_mux_register(sc->clkdom, &super_mux_def[i]);  in tegra124_super_mux_clock()