| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | ti,phy-j721e-wiz.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g
19 - ti,am64-wiz-10g
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| /linux/drivers/gpu/drm/amd/display/dc/dio/dcn30/ |
| H A D | dcn30_dio_link_encoder.c | 36 enc10->base.ctx
38 enc10->base.ctx->logger
41 (enc10->link_regs->reg)
45 enc10->link_shift->field_name, enc10->link_mask->field_name
48 (enc10->link_regs->index)
100 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; in dcn30_link_encoder_construct()
102 struct dcn10_link_encoder *enc10 = &enc20->enc10; in dcn30_link_encoder_construct()
104 enc10->base.funcs = &dcn30_link_enc_funcs; in dcn30_link_encoder_construct()
105 enc10->base.ctx = init_data->ctx; in dcn30_link_encoder_construct()
106 enc10->base.id = init_data->encoder; in dcn30_link_encoder_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn401/ |
| H A D | dcn401_dccg.c | 44 (dccg_dcn->regs->reg)
48 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
51 dccg_dcn->base.ctx
53 dccg->ctx->logger
81 if (dccg->ref_dppclk && req_dppclk) { in dccg401_update_dpp_dto()
82 int ref_dppclk = dccg->ref_dppclk; in dccg401_update_dpp_dto()
87 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg401_update_dpp_dto()
102 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg401_update_dpp_dto()
106 * without the probability of causing a DIG FIFO error.
225 if (src == REFCLK) in dccg401_set_dtbclk_p_src()
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| /linux/drivers/gpu/drm/amd/display/dc/dio/dcn20/ |
| H A D | dcn20_link_encoder.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
37 enc10->base.ctx
39 enc10->base.ctx->logger
42 (enc10->link_regs->reg)
46 enc10->link_shift->field_name, enc10->link_mask->field_name
49 (enc10->link_regs->index)
177 enable ? "Enabling" : "Disabling", enc->id.enum_id); in enc2_fec_set_enable()
205 REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en); in link_enc2_read_state()
206 REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow); in link_enc2_read_state()
207 REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status); in link_enc2_read_state()
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| /linux/drivers/gpu/drm/amd/display/dc/dio/dcn31/ |
| H A D | dcn31_dio_link_encoder.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
43 enc10->base.ctx
45 enc10->base.ctx->logger
48 (enc10->link_regs->reg)
52 enc10->link_shift->field_name, enc10->link_mask->field_name
55 (enc10->link_regs->index)
58 (enc10->aux_regs->reg)
105 struct dc_dmub_srv *dc_dmub_srv = enc->ctx->dmub_srv; in has_query_dp_alt()
107 if (enc->ctx->dce_version >= DCN_VERSION_3_15) in has_query_dp_alt()
112 !(dc_dmub_srv->dmub->fw_version >= DMUB_FW_VERSION(4, 0, 0) && in has_query_dp_alt()
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_dpms.c | 31 * TODO - The reason link owns stream's dpms programming sequence is
83 for (i = 0; i < dc->link_count; i++) { in link_blank_all_dp_displays()
84 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || in link_blank_all_dp_displays()
85 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) in link_blank_all_dp_displays()
89 dp_retrieve_lttpr_cap(dc->links[i]); in link_blank_all_dp_displays()
91 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, in link_blank_all_dp_displays()
95 link_blank_dp_stream(dc->links[i], true); in link_blank_all_dp_displays()
106 for (i = 0; i < dc->link_count; i++) { in link_blank_all_edp_displays()
107 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || in link_blank_all_edp_displays()
108 (!dc->links[i]->edp_sink_present)) in link_blank_all_edp_displays()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 61 for (i = 0; i < context->stream_count; i++) { in rn_get_active_display_cnt_wa()
62 const struct dc_stream_state *stream = context->streams[i]; in rn_get_active_display_cnt_wa()
64 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || in rn_get_active_display_cnt_wa()
65 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || in rn_get_active_display_cnt_wa()
66 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) in rn_get_active_display_cnt_wa()
70 for (i = 0; i < dc->link_count; i++) { in rn_get_active_display_cnt_wa()
71 const struct dc_link *link = dc->links[i]; in rn_get_active_display_cnt_wa()
73 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */ in rn_get_active_display_cnt_wa()
74 if (link->link_enc->funcs->is_dig_enabled && in rn_get_active_display_cnt_wa()
75 link->link_enc->funcs->is_dig_enabled(link->link_enc)) in rn_get_active_display_cnt_wa()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 70 for (i = 0; i < context->stream_count; i++) { in vg_get_active_display_cnt_wa()
71 const struct dc_stream_state *stream = context->streams[i]; in vg_get_active_display_cnt_wa()
73 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || in vg_get_active_display_cnt_wa()
74 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || in vg_get_active_display_cnt_wa()
75 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) in vg_get_active_display_cnt_wa()
79 for (i = 0; i < dc->link_count; i++) { in vg_get_active_display_cnt_wa()
80 const struct dc_link *link = dc->links[i]; in vg_get_active_display_cnt_wa()
82 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */ in vg_get_active_display_cnt_wa()
83 if (link->link_enc->funcs->is_dig_enabled && in vg_get_active_display_cnt_wa()
84 link->link_enc->funcs->is_dig_enabled(link->link_enc)) in vg_get_active_display_cnt_wa()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| H A D | dcn32_hwseq.c | 59 hws->ctx
61 hws->regs->reg
63 dc->ctx->logger
67 hws->shifts->field_name, hws->masks->field_name
77 struct dc *dc = hws->ctx->dc; in dcn32_dsc_pg_control()
79 if (dc->debug.disable_dsc_power_gate) in dcn32_dsc_pg_control()
82 if (!dc->debug.enable_double_buffered_dsc_pg_support) in dcn32_dsc_pg_control()
168 if (hws->ctx->dc->debug.disable_hubp_power_gate) in dcn32_hubp_pg_control()
201 /* First, check no-memory-request case */ in dcn32_check_no_memory_request_for_cab()
202 for (i = 0; i < dc->current_state->stream_count; i++) { in dcn32_check_no_memory_request_for_cab()
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | atombios.h | 2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
815 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
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| /linux/drivers/gpu/drm/amd/include/ |
| H A D | atombios.h | 2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 52 clk_mgr->base.base.ctx->logger
123 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
126 (clk_mgr->regs->reg)
162 for (i = 0; i < context->stream_count; i++) { in dcn35_get_active_display_cnt_wa()
163 const struct dc_stream_state *stream = context->streams[i]; in dcn35_get_active_display_cnt_wa()
165 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || in dcn35_get_active_display_cnt_wa()
166 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || in dcn35_get_active_display_cnt_wa()
167 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) in dcn35_get_active_display_cnt_wa()
171 for (i = 0; i < dc->link_count; i++) { in dcn35_get_active_display_cnt_wa()
172 const struct dc_link *link = dc->links[i]; in dcn35_get_active_display_cnt_wa()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 1 // SPDX-License-Identifier: MIT
41 hws->ctx
43 hws->regs->reg
45 dc->ctx->logger
50 hws->shifts->field_name, hws->masks->field_name
54 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn401_initialize_min_clocks()
56 clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ; in dcn401_initialize_min_clocks()
57 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn401_initialize_min_clocks()
58 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn401_initialize_min_clocks()
59 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn401_initialize_min_clocks()
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