| /linux/Documentation/devicetree/bindings/net/ |
| H A D | nxp,tja11xx.yaml | 52 The REF_CLK is provided for both transmitted and received data
56 connected to pin REF_CLK. A third option is to connect a 25MHz
57 clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
59 If present, indicates that the REF_CLK will be configured as
61 If not present, the REF_CLK will be configured as interface
79 description: Enable 50MHz RMII reference clock output on REF_CLK pin.
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| /linux/drivers/clk/imx/ |
| H A D | clk-pllv2.c | 81 long mfi, mfn, mfd, pdf, ref_clk; in __clk_pllv2_recalc_rate() local
94 ref_clk = 2 * parent_rate; in __clk_pllv2_recalc_rate()
96 ref_clk *= 2; in __clk_pllv2_recalc_rate()
98 ref_clk /= (pdf + 1); in __clk_pllv2_recalc_rate()
99 temp = (u64) ref_clk * abs(mfn); in __clk_pllv2_recalc_rate()
102 temp = (ref_clk * mfi) - temp; in __clk_pllv2_recalc_rate()
104 temp = (ref_clk * mfi) + temp; in __clk_pllv2_recalc_rate()
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| /linux/drivers/clk/ |
| H A D | clk-cs2000-cp.c | 75 #define REF_CLK 1 macro
106 struct clk *ref_clk; member
425 * In static mode, CLK_IN is ignored, so we return REF_CLK instead. in cs2000_get_parent()
427 return priv->dynamic_mode ? CLK_IN : REF_CLK; in cs2000_get_parent()
442 struct clk *clk_in, *ref_clk; in cs2000_clk_get() local
449 ref_clk = devm_clk_get(dev, "ref_clk"); in cs2000_clk_get()
451 if (IS_ERR(ref_clk)) in cs2000_clk_get()
455 priv->ref_clk = ref_clk; in cs2000_clk_get()
486 ref_clk_rate = clk_get_rate(priv->ref_clk); in cs2000_clk_register()
506 parent_names[REF_CLK] = __clk_get_name(priv->ref_clk); in cs2000_clk_register()
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| /linux/drivers/phy/hisilicon/ |
| H A D | phy-hisi-inno-usb2.c | 52 struct clk *ref_clk; member
100 ret = clk_prepare_enable(priv->ref_clk); in hisi_inno_phy_init()
124 clk_disable_unprepare(priv->ref_clk); in hisi_inno_phy_exit()
154 priv->ref_clk = devm_clk_get(dev, NULL); in hisi_inno_phy_probe()
155 if (IS_ERR(priv->ref_clk)) in hisi_inno_phy_probe()
156 return PTR_ERR(priv->ref_clk); in hisi_inno_phy_probe()
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| H A D | phy-histb-combphy.c | 48 struct clk *ref_clk; member
121 ret = clk_prepare_enable(priv->ref_clk); in histb_combphy_init()
154 clk_disable_unprepare(priv->ref_clk); in histb_combphy_exit()
244 priv->ref_clk = devm_clk_get(dev, NULL); in histb_combphy_probe()
245 if (IS_ERR(priv->ref_clk)) { in histb_combphy_probe()
247 return PTR_ERR(priv->ref_clk); in histb_combphy_probe()
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| /linux/include/linux/platform_data/ |
| H A D | net-cw1200.h | 13 u16 ref_clk; /* REQUIRED (in KHz) */ member
26 u16 ref_clk; /* REQUIRED (in KHz) */ member
44 .ref_clk = 38400,
67 .ref_clk = 38400,
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| /linux/drivers/phy/samsung/ |
| H A D | phy-samsung-usb2.c | 36 ret = clk_prepare_enable(drv->ref_clk); in samsung_usb2_phy_power_on()
50 clk_disable_unprepare(drv->ref_clk); in samsung_usb2_phy_power_on()
75 clk_disable_unprepare(drv->ref_clk); in samsung_usb2_phy_power_off()
199 drv->ref_clk = devm_clk_get(dev, "ref"); in samsung_usb2_phy_probe()
200 if (IS_ERR(drv->ref_clk)) { in samsung_usb2_phy_probe()
202 return PTR_ERR(drv->ref_clk); in samsung_usb2_phy_probe()
205 drv->ref_rate = clk_get_rate(drv->ref_clk); in samsung_usb2_phy_probe()
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| /linux/drivers/rtc/ |
| H A D | rtc-cadence.c | 82 struct clk *ref_clk; member
281 crtc->ref_clk = devm_clk_get(&pdev->dev, "ref_clk"); in cdns_rtc_probe()
282 if (IS_ERR(crtc->ref_clk)) { in cdns_rtc_probe()
283 ret = PTR_ERR(crtc->ref_clk); in cdns_rtc_probe()
302 ret = clk_prepare_enable(crtc->ref_clk); in cdns_rtc_probe()
309 ref_clk_freq = clk_get_rate(crtc->ref_clk); in cdns_rtc_probe()
349 clk_disable_unprepare(crtc->ref_clk); in cdns_rtc_probe()
365 clk_disable_unprepare(crtc->ref_clk); in cdns_rtc_remove()
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| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | amlogic,g12a-usb3-pcie-phy.yaml | 26 - const: ref_clk
59 clocks = <&ref_clk>;
60 clock-names = "ref_clk";
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| /linux/drivers/phy/ |
| H A D | phy-snps-eusb2.c | 166 struct clk *ref_clk; member
248 unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk); in exynos_eusb2_ref_clk_init()
285 unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk); in qcom_eusb2_ref_clk_init()
330 /* update ref_clk related registers */ in exynos_snps_eusb2_hsphy_init()
387 /* update ref_clk related registers */ in qcom_snps_eusb2_hsphy_init()
565 phy->ref_clk = NULL; in snps_eusb2_hsphy_probe()
568 phy->ref_clk = phy->clks[i].clk; in snps_eusb2_hsphy_probe()
573 if (IS_ERR_OR_NULL(phy->ref_clk)) { in snps_eusb2_hsphy_probe()
574 ret = phy->ref_clk ? PTR_ERR(phy->ref_clk) : -ENOENT; in snps_eusb2_hsphy_probe()
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| /linux/drivers/phy/qualcomm/ |
| H A D | phy-qcom-ipq806x-usb.c | 122 struct clk *ref_clk; member
262 ret = clk_prepare_enable(phy_dwc3->ref_clk); in qcom_ipq806x_usb_hs_phy_init()
295 clk_disable_unprepare(phy_dwc3->ref_clk); in qcom_ipq806x_usb_hs_phy_exit()
311 ret = clk_prepare_enable(phy_dwc3->ref_clk); in qcom_ipq806x_usb_ss_phy_init()
448 clk_disable_unprepare(phy_dwc3->ref_clk); in qcom_ipq806x_usb_ss_phy_exit()
509 phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref"); in qcom_ipq806x_usb_phy_probe()
510 if (IS_ERR(phy_dwc3->ref_clk)) { in qcom_ipq806x_usb_phy_probe()
512 return PTR_ERR(phy_dwc3->ref_clk); in qcom_ipq806x_usb_phy_probe()
515 clk_set_rate(phy_dwc3->ref_clk, data->clk_rate); in qcom_ipq806x_usb_phy_probe()
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| H A D | phy-qcom-qusb2.c | 448 * @ref_clk: phy reference clock
468 struct clk *ref_clk; member
700 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_runtime_suspend()
734 ret = clk_prepare_enable(qphy->ref_clk); in qusb2_phy_runtime_resume()
839 * ref_clk and use single-ended clock, otherwise use differential in qusb2_phy_init()
840 * ref_clk only. in qusb2_phy_init()
862 ret = clk_prepare_enable(qphy->ref_clk); in qusb2_phy_init()
898 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_init()
920 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_exit()
1026 qphy->ref_clk = devm_clk_get(dev, "ref"); in qusb2_phy_probe()
[all …]
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| /linux/drivers/phy/mediatek/ |
| H A D | phy-mtk-mipi-dsi.c | 110 struct clk *ref_clk; in mtk_mipi_tx_probe() local
132 ref_clk = devm_clk_get(dev, NULL); in mtk_mipi_tx_probe()
133 if (IS_ERR(ref_clk)) in mtk_mipi_tx_probe()
134 return dev_err_probe(dev, PTR_ERR(ref_clk), in mtk_mipi_tx_probe()
151 ref_clk_name = __clk_get_name(ref_clk); in mtk_mipi_tx_probe()
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| /linux/drivers/phy/starfive/ |
| H A D | phy-jh7110-dphy-rx.c | 65 struct clk *ref_clk; member
123 clk_set_rate(dphy->ref_clk, 49500000); in stf_dphy_power_on()
172 dphy->ref_clk = devm_clk_get(&pdev->dev, "ref"); in stf_dphy_probe()
173 if (IS_ERR(dphy->ref_clk)) in stf_dphy_probe()
174 return PTR_ERR(dphy->ref_clk); in stf_dphy_probe()
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| /linux/Documentation/devicetree/bindings/ufs/ |
| H A D | qcom,ufs.yaml | 84 - const: ref_clk
115 - const: ref_clk
142 - const: ref_clk
225 "ref_clk",
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| H A D | renesas,ufs.yaml | 28 - const: ref_clk
67 clock-names = "fck", "ref_clk";
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| H A D | hisilicon,ufs.yaml | 43 - const: ref_clk
83 clock-names = "ref_clk", "phy_clk";
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| /linux/Documentation/devicetree/bindings/rtc/ |
| H A D | cdns,rtc.txt | 12 - ref_clk: reference 1Hz or 100Hz clock, depending on IP configuration
20 clock-names = "pclk", "ref_clk";
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| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | jcore,spi.txt | 15 - clocks: If a phandle named "ref_clk" is present, SPI clock speed
33 clock-names = "ref_clk";
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| H A D | xlnx,zynq-qspi.yaml | 37 - const: ref_clk
56 clock-names = "ref_clk", "pclk";
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| H A D | spi-zynqmp-qspi.yaml | 27 - const: ref_clk
75 clock-names = "ref_clk", "pclk";
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| /linux/drivers/net/wireless/ath/ath10k/ |
| H A D | ahb.c | 96 ar_ahb->ref_clk = devm_clk_get(dev, "wifi_wcss_ref"); in ath10k_ahb_clock_init()
97 if (IS_ERR(ar_ahb->ref_clk)) { in ath10k_ahb_clock_init()
99 PTR_ERR(ar_ahb->ref_clk)); in ath10k_ahb_clock_init()
100 return PTR_ERR(ar_ahb->ref_clk); in ath10k_ahb_clock_init()
118 ar_ahb->ref_clk = NULL; in ath10k_ahb_clock_deinit()
128 IS_ERR_OR_NULL(ar_ahb->ref_clk) || in ath10k_ahb_clock_enable()
141 ret = clk_prepare_enable(ar_ahb->ref_clk); in ath10k_ahb_clock_enable()
156 clk_disable_unprepare(ar_ahb->ref_clk); in ath10k_ahb_clock_enable()
171 clk_disable_unprepare(ar_ahb->ref_clk); in ath10k_ahb_clock_disable()
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| /linux/Documentation/devicetree/bindings/fpga/ |
| H A D | xilinx-zynq-fpga-mgr.yaml | 27 - const: ref_clk
50 clock-names = "ref_clk";
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| /linux/drivers/spi/ |
| H A D | spi-cadence.c | 104 * @ref_clk: Pointer to the peripheral clock
106 * @clk_rate: Reference clock frequency, taken from @ref_clk
120 struct clk *ref_clk; member
681 xspi->ref_clk = devm_clk_get_enabled(&pdev->dev, "ref_clk"); in cdns_spi_probe()
682 if (IS_ERR(xspi->ref_clk)) { in cdns_spi_probe()
683 dev_err(&pdev->dev, "ref_clk clock not found.\n"); in cdns_spi_probe()
684 return PTR_ERR(xspi->ref_clk); in cdns_spi_probe()
741 xspi->clk_rate = clk_get_rate(xspi->ref_clk); in cdns_spi_probe()
854 ret = clk_prepare_enable(xspi->ref_clk); in cdns_spi_runtime_resume()
876 clk_disable_unprepare(xspi->ref_clk); in cdns_spi_runtime_suspend()
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| /linux/drivers/iio/adc/ |
| H A D | ad7625.c | 186 * the duty_cycle for ref_clk, cnv, and clk_gate in ad7625_set_sampling_freq()
460 struct clk *ref_clk; in devm_ad7625_pwm_get() local
479 ref_clk = devm_clk_get_enabled(dev, NULL); in devm_ad7625_pwm_get()
480 if (IS_ERR(ref_clk)) in devm_ad7625_pwm_get()
481 return dev_err_probe(dev, PTR_ERR(ref_clk), in devm_ad7625_pwm_get()
482 "failed to get ref_clk\n"); in devm_ad7625_pwm_get()
484 ref_clk_rate_hz = clk_get_rate(ref_clk); in devm_ad7625_pwm_get()
487 "failed to get ref_clk rate\n"); in devm_ad7625_pwm_get()
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