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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Darm,pl172.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl172.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
18 - arm,pl172
19 - arm,pl175
20 - arm,pl176
22 - compatible
27 - enum:
[all …]
H A Dmvebu-devbus.txt9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
28 - devbus,keep-config This property can optionally be used to keep
35 Read parameters:
[all …]
H A Dst,stm32-fmc2-ebi-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Marek Vasut <marex@denx.de>
14 st,fmc2-ebi-cs-transaction-type:
25 8: Synchronous read synchronous write PSRAM.
26 9: Synchronous read asynchronous write PSRAM.
27 10: Synchronous read synchronous write NOR.
[all …]
/linux/drivers/iio/imu/
H A Dadis.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/delay.h>
27 * __adis_write_reg() - write N bytes to register (unlocked version)
41 .tx_buf = adis->tx, in __adis_write_reg()
44 .delay.value = adis->data->write_delay, in __adis_write_reg()
45 .delay.unit = SPI_DELAY_UNIT_USECS, in __adis_write_reg()
47 .tx_buf = adis->tx + 2, in __adis_write_reg()
50 .delay.value = adis->data->write_delay, in __adis_write_reg()
51 .delay.unit = SPI_DELAY_UNIT_USECS, in __adis_write_reg()
[all …]
/linux/tools/testing/selftests/thermal/intel/workload_hint/
H A Dworkload_hint_test.c1 // SPDX-License-Identifier: GPL-2.0
35 perror("Unable to open workload type feature enable file"); in workload_hint_exit()
55 int delay = 0; in main() local
57 printf("Usage: workload_hint_test [notification delay in milli seconds]\n"); in main()
60 ret = sscanf(argv[1], "%d", &delay); in main()
62 printf("Invalid delay\n"); in main()
66 printf("Setting notification delay to %d ms\n", delay); in main()
[all...]
/linux/drivers/misc/eeprom/
H A Deeprom_93cx6.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2004 - 2006 rt2x00 SourceForge Project
14 #include <linux/delay.h>
24 eeprom->reg_data_clock = 1; in eeprom_93cx6_pulse_high()
25 eeprom->register_write(eeprom); in eeprom_93cx6_pulse_high()
28 * Add a short delay for the pulse to work. in eeprom_93cx6_pulse_high()
37 eeprom->reg_data_clock = 0; in eeprom_93cx6_pulse_low()
38 eeprom->register_write(eeprom); in eeprom_93cx6_pulse_low()
41 * Add a short delay for the pulse to work. in eeprom_93cx6_pulse_low()
51 * Clear all flags, and enable chip select. in eeprom_93cx6_startup()
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dsprd,sdhci-r11.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/sprd,sdhci-r11.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
16 const: sprd,sdhci-r11
27 - description: SDIO source clock
28 - description: gate clock for enabling/disabling the device
[all …]
/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
12 /* [15:0] The Version register for H264 core (Read Only) */
19 /* Enable bit for Inter module */
21 /* Enable bit for Sensor Interface module */
23 /* Enable bit for Host Burst Access */
25 /* Enable bit for Loop Filter module */
[all …]
/linux/arch/mips/sgi-ip22/
H A Dip22-nvram.c1 // SPDX-License-Identifier: GPL-2.0
3 * ip22-nvram.c: NVRAM and serial EEPROM handling.
5 * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org)
13 #define EEPROM_READ 0xc000 /* serial memory read */
14 #define EEPROM_WEN 0x9800 /* write enable before prog modes */
18 #define EEPROM_PRREAD 0xc000 /* read protect register */
19 #define EEPROM_PREN 0x9800 /* enable protect register mode */
24 #define EEPROM_EPROT 0x01 /* Protect register enable */
31 #define delay() ({ \ macro
39 delay(); \
[all …]
/linux/Documentation/driver-api/thermal/
H A Dintel_dptf.rst1 .. SPDX-License-Identifier: GPL-2.0
12 ------------
26 "Linux Thermal Daemon" to read platform specific thermal and power
31 ----------------------------
43 "42A441D6-AE6A-462b-A84B-4A8CE79027D3" : Passive 1
45 "3A95C389-E4B8-4629-A526-C52C88626BAE" : Active
47 "97C68AE7-15FA-499c-B8C9-5DA81D606E0A" : Critical
49 "63BE270F-1C11-48FD-A6F7-3AF253FF3E2D" : Adaptive performance
51 "5349962F-71E6-431D-9AE8-0A635B710AEE" : Emergency call
53 "9E04115A-AE87-4D1C-9500-0F3E340BFE75" : Passive 2
[all …]
/linux/drivers/regulator/
H A Danatop-regulator.c1 // SPDX-License-Identifier: GPL-2.0+
43 if (anatop_reg->delay_bit_width && new_sel > old_sel) { in anatop_regmap_set_voltage_time_sel()
45 * the delay for LDO ramp up time is in anatop_regmap_set_voltage_time_sel()
48 * ramp up, and how much delay needed. (us) in anatop_regmap_set_voltage_time_sel()
50 regmap_read(reg->regmap, anatop_reg->delay_reg, &val); in anatop_regmap_set_voltage_time_sel()
51 val = (val >> anatop_reg->delay_bit_shift) & in anatop_regmap_set_voltage_time_sel()
52 ((1 << anatop_reg->delay_bit_width) - 1); in anatop_regmap_set_voltage_time_sel()
53 ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES << in anatop_regmap_set_voltage_time_sel()
65 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel; in anatop_regmap_enable()
85 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) { in anatop_regmap_core_set_voltage_sel()
[all …]
/linux/include/soc/at91/
H A Dat91sam9_ddrsdr.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
46 #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
48 #define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Onl…
51 #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
52 #define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
53 #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
54 #define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
55 #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
57 #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
58 #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
[all …]
/linux/lib/
H A DKconfig.kcsan1 # SPDX-License-Identifier: GPL-2.0-only
7 def_bool (CC_IS_CLANG && $(cc-option,-fsanitize=thread -mllvm -tsan-distinguish-volatil
[all...]
/linux/drivers/hid/intel-thc-hid/intel-thc/
H A Dintel-thc-dev.c1 /* SPDX-License-Identifier: GPL-2.0 */
9 #include "intel-thc-dev.h"
10 #include "intel-thc-hw.h"
16 void __iomem *base = thc_ctx->mmio_addr; in thc_regmap_read()
26 void __iomem *base = thc_ctx->mmio_addr; in thc_regmap_write()
58 * thc_clear_state - Clear THC hardware state
71 regmap_write_bits(dev->thc_regmap, THC_M_PRT_ERR_CAUSE_OFFSET, val, val); in thc_clear_state()
74 regmap_write_bits(dev->thc_regmap, THC_M_PRT_READ_DMA_CNTRL_1_OFFSET, in thc_clear_state()
77 regmap_write_bits(dev->thc_regmap, THC_M_PRT_READ_DMA_CNTRL_2_OFFSET, in thc_clear_state()
81 regmap_write_bits(dev->thc_regmap, THC_M_PRT_INT_STATUS_OFFSET, in thc_clear_state()
[all …]
/linux/arch/arm/mach-mmp/
H A Dtime.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-mmp/time.c
10 * 2008-04-11: Jason Chagas <Jason.chagas@marvell.com>
11 * 2008-10-08: Bin Yang <bin.yang@marvell.com>
14 * three match comparators. Timer #0 is used here in free-running mode as
32 #include "regs-timers.h"
41 * Read the timer through the CVWR register. Delay is required after requesting
42 * a read. The CR register cannot be directly read due to metastability issues
48 int delay = 3; in timer_read() local
52 while (delay--) in timer_read()
[all …]
/linux/drivers/net/ethernet/realtek/
H A Datp.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 ushort rx_status; /* Unknown bit assignments :-<. */
29 #define WrAddr 0x40 /* Set address of EPLC read, write register. */
60 #define CMR1h_RxENABLE 0x02 /* Rx unit enable. */
61 #define CMR1h_TxENABLE 0x01 /* Tx unit enable. */
66 #define CMR1_BufEnb 0x01 /* Enable the buffer(?). */
67 #define CMR1_NextPkt 0x01 /* Enable the buffer(?). */
90 /* Read register OFFSET.
99 inbyte(port + PAR_STATUS); /* Settling time delay */ in read_nibble()
106 /* Functions for bulk data read. The interrupt line is always disabled. */
[all …]
/linux/drivers/rtc/
H A Drtc-max77686.c1 // SPDX-License-Identifier: GPL-2.0+
7 // based on rtc-max8997.c
12 #include <linux/delay.h>
16 #include <linux/mfd/max77686-private.h>
23 #define MAX77686_INVALID_I2C_ADDR (-1)
26 #define MAX77686_INVALID_REG (-1)
38 /* RTC Alarm Enable */
45 * MAX77802 has separate register (RTCAE1) for alarm enable instead
63 * struct max77686_rtc_driver_data - model-specific configuration
64 * @delay: Minimum usecs needed for a RTC update
[all …]
/linux/drivers/iio/common/ms_sensors/
H A Dms_sensors_i2c.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2015 Measurement-Specialties
11 #include <linux/delay.h>
38 * ms_sensors_reset() - Reset function
41 * @delay: usleep minimal delay after reset command is issued
47 int ms_sensors_reset(void *cli, u8 cmd, unsigned int delay) in ms_sensors_reset() argument
54 dev_err(&client->dev, "Failed to reset device\n"); in ms_sensors_reset()
57 usleep_range(delay, delay + 1000); in ms_sensors_reset()
64 * ms_sensors_read_prom_word() - PROM word read function
66 * @cmd: PROM read cmd. Depends on device and prom id
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra210-p2180.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/mfd/max77620.h>
18 stdout-path = "serial0:115200n8";
27 vdd-supply = <&vdd_gpu>;
33 /delete-property/ dmas;
34 /delete-property/ dma-names;
39 /delete-property/ reg-shift;
41 compatible = "nvidia,tegra30-hsuart";
42 reset-names = "serial";
45 compatible = "brcm,bcm43540-bt";
[all …]
/linux/drivers/net/ethernet/oki-semi/pch_gbe/
H A Dpch_gbe_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1999 - 2010 Intel Corporation.
12 #define PHY_MAX_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
25 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Register */
26 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Register */
35 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
40 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
71 #define PHY_AR8031_SERDES_TX_CLK_DLY 0x0100 /* TX clock delay of 2.0ns */
72 #define PHY_AR8031_PS_HIB_EN 0x8000 /* Hibernate enable */
85 #define PHY_1000T_CTRL_DEFAULT 0x0300 /* 1000Base-T Control Register */
[all …]
/linux/arch/arm/include/asm/hardware/
H A Dlocomo.h38 #define LOCOMO_ASD 0x20 /* AD start delay */
39 #define LOCOMO_HSD 0x28 /* HSYS delay */
53 #define LOCOMO_DAC_SDA 0x02 /* SDA pin level (read-only) */
64 #define LOCOMO_SPI_RFR (1) /* read buffer bit */
67 #define LOCOMO_SPIWE 0x14 /* SPI interrupt status write enable */
68 #define LOCOMO_SPIIE 0x18 /* SPI interrupt enable */
71 #define LOCOMO_SPIRD 0x24 /* SPI receive data read */
77 #define LOCOMO_GPE 0x94 /* GPIO input enable */
83 #define LOCOMO_GWE 0xac /* GPIO status write enable */
84 #define LOCOMO_GIE 0xb0 /* GPIO interrupt enable */
[all …]
/linux/drivers/net/dsa/qca/
H A Dqca8k-8xxx.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
47 ret = bus->write(bus, phy_id, regnum, lo); in qca8k_mii_write_lo()
49 dev_err_ratelimited(&bus->dev, in qca8k_mii_write_lo()
62 ret = bus->write(bus, phy_id, regnum, hi); in qca8k_mii_write_hi()
64 dev_err_ratelimited(&bus->dev, in qca8k_mii_write_hi()
75 ret = bus->read(bus, phy_id, regnum); in qca8k_mii_read_lo()
83 dev_err_ratelimited(&bus->dev, in qca8k_mii_read_lo()
84 "failed to read qca8k 32bit lo register\n"); in qca8k_mii_read_lo()
95 ret = bus->read(bus, phy_id, regnum); in qca8k_mii_read_hi()
[all …]
/linux/include/linux/
H A Drmi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2011-2016 Synaptics Incorporated
21 * struct rmi_2d_axis_alignment - target axis alignment
22 * @swap_axes: set to TRUE if desired to swap x- and y-axis
23 * @flip_x: set to TRUE if desired to flip direction on x-axis
24 * @flip_y: set to TRUE if desired to flip direction on y-axis
25 * @clip_x_low - reported X coordinates below this setting will be clipped to
27 * @clip_x_high - reported X coordinates above this setting will be clipped to
29 * @clip_y_low - reported Y coordinates below this setting will be clipped to
31 * @clip_y_high - reported Y coordinates above this setting will be clipped to
[all …]
/linux/drivers/net/phy/
H A Dbroadcom.c1 // SPDX-License-Identifier: GPL-2.0+
8 * Broadcom BCM54810, BCM54811 BroadR-Reach transceivers.
15 #include "bcm-phy-lib.h"
16 #include <linux/delay.h>
27 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
54 /* Long-Distance Signaling (BroadR-Reach mode aneg) relevant linkmode bits */
65 struct bcm54xx_phy_priv *priv = phydev->priv; in bcm54xx_phy_can_wakeup()
67 return phy_interrupt_is_valid(phydev) || priv->wake_irq >= 0; in bcm54xx_phy_can_wakeup()
74 /* handling PHY's internal RX clock delay */ in bcm54xx_config_clock_delay()
77 if (phydev->interface == PHY_INTERFACE_MODE_RGMII || in bcm54xx_config_clock_delay()
[all …]
/linux/tools/power/pm-graph/config/
H A Dexample.cfg9 # sudo ./sleepgraph.py -config config/example.cfg
14 # ---- General Options ----
26 output-dir: suspend-{hostname}-{date}-{time}
48 # Runtime suspend enable/disable
49 # Enable/disable runtime suspend for all devices, restore all after test (default: no-action)
53 # Switch the display on/off for the test using xset (default: no-action)
57 # Print the status of the test run in the given file (default: no-action)
61 # Gzip the generated log files, and read gzipped log files (default: false)
64 # ---- Advanced Options ----
85 # Back to Back Suspend Delay
[all …]

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