Lines Matching +full:read +full:- +full:enable +full:- +full:delay

1 /* SPDX-License-Identifier: GPL-2.0 */
12 	ushort rx_status;	/* Unknown bit assignments :-<.  */
29 #define WrAddr	0x40	/* Set address of EPLC read, write register. */
60 #define CMR1h_RxENABLE	0x02	/* Rx unit enable.  */
61 #define CMR1h_TxENABLE	0x01	/* Tx unit enable.  */
66 #define	CMR1_BufEnb	0x01	/* Enable the buffer(?). */
67 #define	CMR1_NextPkt	0x01	/* Enable the buffer(?). */
90 /* Read register OFFSET.
99 	inbyte(port + PAR_STATUS);	/* Settling time delay */  in read_nibble()
106 /* Functions for bulk data read.  The interrupt line is always disabled. */
107 /* Get a byte using read mode 0, reading data from the control lines. */
116 	inbyte(ioaddr + PAR_STATUS);	/* Settling time delay -- needed!  */  in read_byte_mode0()
117 	inbyte(ioaddr + PAR_STATUS);	/* Settling time delay -- needed!  */  in read_byte_mode0()
130 	inbyte(ioaddr + PAR_STATUS);	/* Settling time delay -- needed!  */  in read_byte_mode2()
134 /* Read a byte through the data register. */
145 /* Read a byte through the data register, double reading to allow settling. */
258 /* The EEPROM commands include the alway-set leading bit. */