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/linux/Documentation/devicetree/bindings/sound/
H A Dsamsung,aries-wm8994.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/samsung,aries-wm8994.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jonathan Bakker <xc-racer2@live.ca>
13 - $ref: sound-card-common.yaml#
19 - samsung,aries-wm8994
21 - samsung,fascinate4g-wm8994
27 sound-dai:
34 - sound-dai
[all …]
H A Dsamsung,midas-audio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/samsung,midas-audio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - $ref: sound-card-common.yaml#
17 const: samsung,midas-audio
23 sound-dai:
27 - sound-dai
33 sound-dai:
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/linux/include/dt-bindings/pinctrl/
H A Dpinctrl-tegra.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain,
16 * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt.
/linux/sound/soc/codecs/
H A Dmax98095.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * max98095.c -- MAX98095 ALSA SoC Audio driver
338 "Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k",
339 "Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"};
355 unsigned int sel = ucontrol->value.integer.value[0]; in max98095_mic1pre_set() local
357 max98095->mic1pre = sel; in max98095_mic1pre_set()
359 (1+sel)<<M98095_MICPRE_SHIFT); in max98095_mic1pre_set()
370 ucontrol->value.integer.value[0] = max98095->mic1pre; in max98095_mic1pre_get()
379 unsigned int sel = ucontrol->value.integer.value[0]; in max98095_mic2pre_set() local
381 max98095->mic2pre = sel; in max98095_mic2pre_set()
[all …]
H A Dmax98090.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * max98090.c -- MAX98090 ALSA SoC Audio driver
5 * Copyright 2011-2012 Maxim Integrated Products
83 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
84 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
85 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
279 /* Reset the codec by writing to this write-only reset register */ in max98090_reset()
280 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET, in max98090_reset()
283 dev_err(max98090->component->dev, in max98090_reset()
300 -600, 600, 0);
[all …]
H A Dmt6358.c1 // SPDX-License-Identifier: GPL-2.0
3 // mt6358.c -- mt6358 ALSA SoC audio codec driver
107 priv->mtkaif_protocol = mtkaif_protocol; in mt6358_set_mtkaif_protocol()
115 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR, in playback_gpio_set()
117 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_SET, in playback_gpio_set()
119 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2, in playback_gpio_set()
130 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR, in playback_gpio_reset()
132 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2, in playback_gpio_reset()
134 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0, in playback_gpio_reset()
141 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR, in capture_gpio_set()
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra114-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra114-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra114-pinmux
19 - description: pad control registers
20 - description: mux registers
23 "^pinmux(-[a-z0-9-_]+)?$":
[all …]
H A Dnvidia,tegra124-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra124-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 Tegra30 pinctrl binding, as described in nvidia,tegra20-pinmux.yaml and
15 nvidia,tegra30-pinmux.yaml. In fact, this document assumes that binding as a
21 - const: nvidia,tegra124-pinmux
22 - items:
[all …]
H A Dnvidia,tegra-pinmux-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra-pinmux-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
14 Please refer to pinctrl-bindings.txt in this directory for details of the
22 pin configuration parameters, such as pull-up, tristate, drive strength,
46 $ref: /schemas/types.yaml#/definitions/string-array
57 description: Pull-down/up setting to apply to the pin.
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Ds5pv210-fascinate4g.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include "s5pv210-aries.dtsi"
9 model = "Samsung Galaxy S Fascinate 4G (SGH-T959P) based on S5PV210";
11 chassis-type = "handset";
14 stdout-path = &uart2;
17 gpio-keys {
18 compatible = "gpio-keys";
[all …]
H A Ds5pv210-galaxys.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include "s5pv210-aries.dtsi"
9 model = "Samsung Galaxy S1 (GT-I9000) based on S5PV210";
11 chassis-type = "handset";
14 stdout-path = &uart2;
17 nand_pwrseq: nand-pwrseq {
18 compatible = "mmc-pwrseq-simple";
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124-nyan-blaze.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra124-nyan.dtsi"
6 #include "tegra124-nyan-blaze-emc.dtsi"
10 compatible = "google,nyan-blaze-rev10", "google,nyan-blaze-rev9",
11 "google,nyan-blaze-rev8", "google,nyan-blaze-rev7",
12 "google,nyan-blaze-rev6", "google,nyan-blaze-rev5",
13 "google,nyan-blaze-rev4", "google,nyan-blaze-rev3",
14 "google,nyan-blaze-rev2", "google,nyan-blaze-rev1",
15 "google,nyan-blaze-rev0", "google,nyan-blaze",
[all …]
H A Dtegra124-nyan-big.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra124-nyan.dtsi"
6 #include "tegra124-nyan-big-emc.dtsi"
9 model = "Acer Chromebook 13 CB5-311";
10 compatible = "google,nyan-big-rev7", "google,nyan-big-rev6",
11 "google,nyan-big-rev5", "google,nyan-big-rev4",
12 "google,nyan-big-rev3", "google,nyan-big-rev2",
13 "google,nyan-big-rev1", "google,nyan-big-rev0",
14 "google,nyan-big", "google,nyan", "nvidia,tegra124";
[all …]
H A Dtegra124-apalis-v1.2.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2016-2018 Toradex AG
7 #include "tegra124-apalis-emc.dtsi"
21 avddio-pex-supply = <&reg_1v05_vdd>;
22 avdd-pex-pll-supply = <&reg_1v05_vdd>;
23 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
24 dvddio-pex-supply = <&reg_1v05_vdd>;
25 hvdd-pex-pll-e-supply = <&reg_module_3v3>;
26 hvdd-pex-supply = <&reg_module_3v3>;
27 vddio-pex-ctl-supply = <&reg_module_3v3>;
[all …]
H A Dtegra124-jetson-tk1.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
7 #include "tegra124-jetson-tk1-emc.dtsi"
11 compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
17 /* This order keeps the mapping DB9 connector <-> ttyS0 */
24 stdout-path = "serial0:115200n8";
34 avddio-pex-supply = <&vdd_1v05_run>;
35 dvddio-pex-supply = <&vdd_1v05_run>;
36 avdd-pex-pll-supply = <&vdd_1v05_run>;
[all …]
H A Dtegra124-apalis.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
7 #include "tegra124-apalis-emc.dtsi"
20 avddio-pex-supply = <&reg_1v05_vdd>;
21 avdd-pex-pll-supply = <&reg_1v05_vdd>;
22 avdd-pll-erefe-supply = <&reg_1v05_avdd>;
23 dvddio-pex-supply = <&reg_1v05_vdd>;
24 hvdd-pex-pll-e-supply = <&reg_module_3v3>;
25 hvdd-pex-supply = <&reg_module_3v3>;
26 vddio-pex-ctl-supply = <&reg_module_3v3>;
[all …]
H A Dtegra114-roth.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
15 linux,initrd-start = <0x82000000>;
16 linux,initrd-end = <0x82800000>;
24 trusted-foundations {
25 compatible = "tlm,trusted-foundations";
26 tlm,version-major = <2>;
27 tlm,version-minor = <8>;
40 avdd-dsi-csi-supply = <&vdd_1v2_ap>;
[all …]
H A Dtegra124-venice2.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
29 vdd-supply = <&vdd_3v3_hdmi>;
30 pll-supply = <&vdd_hdmi_pll>;
31 hdmi-supply = <&vdd_5v0_hdmi>;
33 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
34 nvidia,hpd-gpio =
41 avdd-io-hdmi-dp-supply = <&vdd_1v05_run>;
[all …]
/linux/sound/soc/samsung/
H A Dmidas_wm1811.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/input-event-codes.h>
17 #include <sound/soc-dapm.h>
77 struct midas_priv *priv = snd_soc_card_get_drvdata(codec->card); in headset_jack_check()
81 if (!gpiod_get_value_cansleep(priv->gpio_headset_detect)) in headset_jack_check()
85 ret = snd_soc_dapm_force_enable_pin(dapm, "headset-mic-bias"); in headset_jack_check()
96 ret = iio_read_channel_processed(priv->adc_headset_detect, &adc); in headset_jack_check()
105 jack_type = snd_soc_jack_get_type(&priv->headset_jack, adc); in headset_jack_check()
108 ret = snd_soc_dapm_disable_pin(dapm, "headset-mic-bias"); in headset_jack_check()
120 struct midas_priv *priv = snd_soc_card_get_drvdata(codec->card); in headset_key_check()
[all …]
H A Daries_wm8994.c1 // SPDX-License-Identifier: GPL-2.0+
5 #include <linux/input-event-codes.h>
98 if (!gpiod_get_value(priv->gpio_headset_detect)) { in headset_det_irq_thread()
101 gpiod_set_value(priv->gpio_earpath_sel, 0); in headset_det_irq_thread()
105 time_left_ms -= 20; in headset_det_irq_thread()
109 ret = regulator_enable(priv->reg_headset_micbias); in headset_det_irq_thread()
113 gpiod_set_value(priv->gpio_earpath_sel, 1); in headset_det_irq_thread()
115 ret = iio_read_channel_processed(priv->adc, &adc); in headset_det_irq_thread()
127 ret = regulator_disable(priv->reg_headset_micbias); in headset_det_irq_thread()
133 gpiod_set_value(priv->gpio_earpath_sel, 0); in headset_det_irq_thread()
[all …]
/linux/include/net/
H A Ddsa.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/net/dsa.h - Driver for Distributed Switch Architecture switch chips
4 * Copyright (c) 2008-2009 Marvell Semiconductor
94 struct sk_buff *(*rcv)(struct sk_buff *skb, struct net_device *dev); member
125 /* Notifier chain for switch-wide events */
134 /* Maps offloaded LAG netdevs to a zero-based linear ID for
166 /* LAG IDs are one-based, the dst->lags array is zero-based */
168 for ((_id) = 1; (_id) <= (_dst)->lags_len; (_id)++) \
169 if ((_dst)->lags[(_id) - 1])
172 list_for_each_entry((_dp), &(_dst)->ports, list) \
[all …]
H A Dipv6.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
34 #define NEXTHDR_HOP 0 /* Hop-by-hop option header. */
55 /* Limits on Hop-by-Hop and Destination options.
58 * Hop-by-Hop or Destination options other then the packet must fit in an MTU.
63 * - Limit the number of options in a Hop-by-Hop or Destination options
65 * - Limit the byte length of a Hop-by-Hop or Destination options extension
67 * - Disallow unknown options
77 * options or Hop-by-Hop options. If the number is less than zero then unknown
82 * Hop-by-Hop options extension header. Setting the value to INT_MAX
89 /* Default limits for Hop-by-Hop and Destination options */
[all …]
/linux/net/tipc/
H A Dnode.c4 * Copyright (c) 2000-2006, 2012-2016, Ericsson AB
5 * Copyright (c) 2005-2006, 2010-2014, Wind River Systems
83 * struct tipc_node - TIPC node structure
103 * @peer_id: 128-bit ID of peer
195 static struct tipc_link *node_active_link(struct tipc_node *n, int sel) in node_active_link() argument
197 int bearer_id = n->active_links[sel & 1]; in node_active_link()
202 return n->links[bearer_id].link; in node_active_link()
205 int tipc_node_get_mtu(struct net *net, u32 addr, u32 sel, bool connected) in tipc_node_get_mtu() argument
218 if (n->peer_net && connected) { in tipc_node_get_mtu()
223 bearer_id = n->active_links[sel & 1]; in tipc_node_get_mtu()
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Dmac.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
41 u32 val, enum rtw89_mac_mem_sel sel) in rtw89_mac_mem_write() argument
43 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; in rtw89_mac_mem_write()
44 u32 addr = mac->mem_base_addrs[sel] + offset; in rtw89_mac_mem_write()
46 rtw89_write32(rtwdev, mac->filter_model_addr, addr); in rtw89_mac_mem_write()
47 rtw89_write32(rtwdev, mac->indir_access_addr, val); in rtw89_mac_mem_write()
51 enum rtw89_mac_mem_sel sel) in rtw89_mac_mem_read() argument
53 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; in rtw89_mac_mem_read()
54 u32 addr = mac->mem_base_addrs[sel] + offset; in rtw89_mac_mem_read()
[all …]
/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
10 * Copyright (C) 2009-2011 ST-Ericsson AB
27 #include "../pinctrl-utils.h"
28 #include "pinctrl-tegra.h"
32 return readl(pmx->regs[bank] + reg); in pmx_readl()
37 writel_relaxed(val, pmx->regs[bank] + reg); in pmx_writel()
46 return pmx->soc->ngroups; in tegra_pinctrl_get_groups_count()
54 return pmx->soc->groups[group].name; in tegra_pinctrl_get_group_name()
64 *pins = pmx->soc->groups[group].pins; in tegra_pinctrl_get_group_pins()
[all …]

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