1*de1835e3SThierry Reding# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*de1835e3SThierry Reding%YAML 1.2 3*de1835e3SThierry Reding--- 4*de1835e3SThierry Reding$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra124-pinmux.yaml# 5*de1835e3SThierry Reding$schema: http://devicetree.org/meta-schemas/core.yaml# 6*de1835e3SThierry Reding 7*de1835e3SThierry Redingtitle: NVIDIA Tegra124 Pinmux Controller 8*de1835e3SThierry Reding 9*de1835e3SThierry Redingmaintainers: 10*de1835e3SThierry Reding - Thierry Reding <thierry.reding@gmail.com> 11*de1835e3SThierry Reding - Jon Hunter <jonathanh@nvidia.com> 12*de1835e3SThierry Reding 13*de1835e3SThierry Redingdescription: The Tegra124 pinctrl binding is very similar to the Tegra20 and 14*de1835e3SThierry Reding Tegra30 pinctrl binding, as described in nvidia,tegra20-pinmux.yaml and 15*de1835e3SThierry Reding nvidia,tegra30-pinmux.yaml. In fact, this document assumes that binding as a 16*de1835e3SThierry Reding baseline, and only documents the differences between the two bindings. 17*de1835e3SThierry Reding 18*de1835e3SThierry Redingproperties: 19*de1835e3SThierry Reding compatible: 20*de1835e3SThierry Reding oneOf: 21*de1835e3SThierry Reding - const: nvidia,tegra124-pinmux 22*de1835e3SThierry Reding - items: 23*de1835e3SThierry Reding - const: nvidia,tegra132-pinmux 24*de1835e3SThierry Reding - const: nvidia,tegra124-pinmux 25*de1835e3SThierry Reding 26*de1835e3SThierry Reding reg: 27*de1835e3SThierry Reding items: 28*de1835e3SThierry Reding - description: driver strength and pad control registers 29*de1835e3SThierry Reding - description: pinmux registers 30*de1835e3SThierry Reding - description: MIPI_PAD_CTRL registers 31*de1835e3SThierry Reding 32*de1835e3SThierry RedingpatternProperties: 33*de1835e3SThierry Reding "^pinmux(-[a-z0-9-_]+)?$": 34*de1835e3SThierry Reding type: object 35*de1835e3SThierry Reding 36*de1835e3SThierry Reding # pin groups 37*de1835e3SThierry Reding additionalProperties: 38*de1835e3SThierry Reding $ref: nvidia,tegra-pinmux-common.yaml 39*de1835e3SThierry Reding additionalProperties: false 40*de1835e3SThierry Reding properties: 41*de1835e3SThierry Reding nvidia,pins: 42*de1835e3SThierry Reding $ref: /schemas/types.yaml#/definitions/string-array 43*de1835e3SThierry Reding items: 44*de1835e3SThierry Reding enum: [ ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3, 45*de1835e3SThierry Reding ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6, 46*de1835e3SThierry Reding ulpi_data6_po7, ulpi_data7_po0, ulpi_clk_py0, ulpi_dir_py1, 47*de1835e3SThierry Reding ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0, dap3_din_pp1, 48*de1835e3SThierry Reding dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0, 49*de1835e3SThierry Reding sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5, 50*de1835e3SThierry Reding sdmmc1_dat1_py6, sdmmc1_dat0_py7, clk2_out_pw5, 51*de1835e3SThierry Reding clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4, ddc_sda_pv5, 52*de1835e3SThierry Reding uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6, 53*de1835e3SThierry Reding uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7, 54*de1835e3SThierry Reding uart3_cts_n_pa1, uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4, 55*de1835e3SThierry Reding pu5, pu6, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5, dap4_fs_pp4, 56*de1835e3SThierry Reding dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, clk3_out_pee0, 57*de1835e3SThierry Reding clk3_req_pee1, pc7, pi5, pi7, pk0, pk1, pj0, pj2, pk3, pk4, 58*de1835e3SThierry Reding pk2, pi3, pi6, pg0, pg1, pg2, pg3, pg4, pg5, pg6, pg7, ph0, 59*de1835e3SThierry Reding ph1, ph2, ph3, ph4, ph5, ph6, ph7, pj7, pb0, pb1, pk7, pi0, 60*de1835e3SThierry Reding pi1, pi2, pi4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6, 61*de1835e3SThierry Reding sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0, 62*de1835e3SThierry Reding sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, 63*de1835e3SThierry Reding sdmmc4_dat4_paa4, sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, 64*de1835e3SThierry Reding sdmmc4_dat7_paa7, cam_mclk_pcc0, pcc1, pbb0, 65*de1835e3SThierry Reding cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, 66*de1835e3SThierry Reding pbb7, pcc2, jtag_rtck, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, 67*de1835e3SThierry Reding kb_row0_pr0, kb_row1_pr1, kb_row2_pr2, kb_row3_pr3, 68*de1835e3SThierry Reding kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7, 69*de1835e3SThierry Reding kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, 70*de1835e3SThierry Reding kb_row12_ps4, kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, 71*de1835e3SThierry Reding kb_col0_pq0, kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, 72*de1835e3SThierry Reding kb_col4_pq4, kb_col5_pq5, kb_col6_pq6, kb_col7_pq7, 73*de1835e3SThierry Reding clk_32k_out_pa0, core_pwr_req, cpu_pwr_req, pwr_int_n, 74*de1835e3SThierry Reding clk_32k_in, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2, 75*de1835e3SThierry Reding dap1_sclk_pn3, dap_mclk1_req_pee2, dap_mclk1_pw4, 76*de1835e3SThierry Reding spdif_in_pk6, spdif_out_pk5, dap2_fs_pa2, dap2_din_pa4, 77*de1835e3SThierry Reding dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0, 78*de1835e3SThierry Reding gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2, 79*de1835e3SThierry Reding gpio_x4_aud_px4, gpio_x5_aud_px5, gpio_x6_aud_px6, 80*de1835e3SThierry Reding gpio_x7_aud_px7, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, 81*de1835e3SThierry Reding sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5, 82*de1835e3SThierry Reding sdmmc3_dat3_pb4, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2, 83*de1835e3SThierry Reding pex_wake_n_pdd3, pex_l1_rst_n_pdd5, pex_l1_clkreq_n_pdd6, 84*de1835e3SThierry Reding hdmi_cec_pee3, sdmmc1_wp_n_pv3, sdmmc3_cd_n_pv2, 85*de1835e3SThierry Reding gpio_w2_aud_pw2, gpio_w3_aud_pw3, usb_vbus_en0_pn4, 86*de1835e3SThierry Reding usb_vbus_en1_pn5, sdmmc3_clk_lb_out_pee4, 87*de1835e3SThierry Reding sdmmc3_clk_lb_in_pee5, gmi_clk_lb, reset_out_n, 88*de1835e3SThierry Reding kb_row16_pt0, kb_row17_pt1, usb_vbus_en2_pff1, pff2, 89*de1835e3SThierry Reding dp_hpd_pff0, 90*de1835e3SThierry Reding # drive groups 91*de1835e3SThierry Reding drive_ao1, drive_ao2, drive_at1, drive_at2, drive_at3, 92*de1835e3SThierry Reding drive_at4, drive_at5, drive_cdev1, drive_cdev2, drive_dap1, 93*de1835e3SThierry Reding drive_dap2, drive_dap3, drive_dap4, drive_dbg, drive_sdio3, 94*de1835e3SThierry Reding drive_spi, drive_uaa, drive_uab, drive_uart2, drive_uart3, 95*de1835e3SThierry Reding drive_sdio1, drive_ddc, drive_gma, drive_gme, drive_gmf, 96*de1835e3SThierry Reding drive_gmg, drive_gmh, drive_owr, drive_uda, drive_gpv, 97*de1835e3SThierry Reding drive_dev3, drive_cec, drive_usb_vbus_en, drive_ao3, 98*de1835e3SThierry Reding drive_ao0, drive_hv0, drive_sdio4, drive_ao4, 99*de1835e3SThierry Reding # MIPI pad control groups 100*de1835e3SThierry Reding mipi_pad_ctrl_dsi_b ] 101*de1835e3SThierry Reding 102*de1835e3SThierry Reding nvidia,function: 103*de1835e3SThierry Reding enum: [ blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, 104*de1835e3SThierry Reding displaya, displaya_alt, displayb, dtv, extperiph1, 105*de1835e3SThierry Reding extperiph2, extperiph3, gmi, gmi_alt, hda, hsi, i2c1, i2c2, 106*de1835e3SThierry Reding i2c3, i2c4, i2cpwr, i2s0, i2s1, i2s2, i2s3, i2s4, irda, kbc, 107*de1835e3SThierry Reding owr, pmi, pwm0, pwm1, pwm2, pwm3, pwron, reset_out_n, rsvd1, 108*de1835e3SThierry Reding rsvd2, rsvd3, rsvd4, sdmmc1, sdmmc2, sdmmc3, sdmmc4, soc, 109*de1835e3SThierry Reding spdif, spi1, spi2, spi3, spi4, spi5, spi6, trace, uarta, 110*de1835e3SThierry Reding uartb, uartc, uartd, ulpi, usb, vgp1, vgp2, vgp3, vgp4, vgp5, 111*de1835e3SThierry Reding vgp6, vi, vi_alt1, vi_alt3, vimclk2, vimclk2_alt, sata, ccla, 112*de1835e3SThierry Reding pe0, pe, pe1, dp, rtck, sys, clk, tmds, csi, dsi_b ] 113*de1835e3SThierry Reding 114*de1835e3SThierry Reding nvidia,pull: true 115*de1835e3SThierry Reding nvidia,tristate: true 116*de1835e3SThierry Reding nvidia,schmitt: true 117*de1835e3SThierry Reding nvidia,pull-down-strength: true 118*de1835e3SThierry Reding nvidia,pull-up-strength: true 119*de1835e3SThierry Reding nvidia,high-speed-mode: true 120*de1835e3SThierry Reding nvidia,low-power-mode: true 121*de1835e3SThierry Reding nvidia,enable-input: true 122*de1835e3SThierry Reding nvidia,open-drain: true 123*de1835e3SThierry Reding nvidia,lock: true 124*de1835e3SThierry Reding nvidia,io-reset: true 125*de1835e3SThierry Reding nvidia,rcv-sel: true 126*de1835e3SThierry Reding nvidia,drive-type: true 127*de1835e3SThierry Reding nvidia,slew-rate-rising: true 128*de1835e3SThierry Reding nvidia,slew-rate-falling: true 129*de1835e3SThierry Reding 130*de1835e3SThierry Reding required: 131*de1835e3SThierry Reding - nvidia,pins 132*de1835e3SThierry Reding 133*de1835e3SThierry RedingadditionalProperties: false 134*de1835e3SThierry Reding 135*de1835e3SThierry Redingrequired: 136*de1835e3SThierry Reding - compatible 137*de1835e3SThierry Reding - reg 138*de1835e3SThierry Reding 139*de1835e3SThierry Redingexamples: 140*de1835e3SThierry Reding - | 141*de1835e3SThierry Reding #include <dt-bindings/clock/tegra124-car.h> 142*de1835e3SThierry Reding #include <dt-bindings/interrupt-controller/arm-gic.h> 143*de1835e3SThierry Reding #include <dt-bindings/pinctrl/pinctrl-tegra.h> 144*de1835e3SThierry Reding 145*de1835e3SThierry Reding pinmux@70000868 { 146*de1835e3SThierry Reding compatible = "nvidia,tegra124-pinmux"; 147*de1835e3SThierry Reding reg = <0x70000868 0x164>, /* Pad control registers */ 148*de1835e3SThierry Reding <0x70003000 0x434>, /* Mux registers */ 149*de1835e3SThierry Reding <0x70000820 0x8>; /* MIPI pad control */ 150*de1835e3SThierry Reding 151*de1835e3SThierry Reding sdmmc4_default: pinmux { 152*de1835e3SThierry Reding sdmmc4_clk_pcc4 { 153*de1835e3SThierry Reding nvidia,pins = "sdmmc4_clk_pcc4"; 154*de1835e3SThierry Reding nvidia,function = "sdmmc4"; 155*de1835e3SThierry Reding nvidia,pull = <TEGRA_PIN_PULL_NONE>; 156*de1835e3SThierry Reding nvidia,tristate = <TEGRA_PIN_DISABLE>; 157*de1835e3SThierry Reding }; 158*de1835e3SThierry Reding 159*de1835e3SThierry Reding sdmmc4_dat0_paa0 { 160*de1835e3SThierry Reding nvidia,pins = "sdmmc4_dat0_paa0", 161*de1835e3SThierry Reding "sdmmc4_dat1_paa1", 162*de1835e3SThierry Reding "sdmmc4_dat2_paa2", 163*de1835e3SThierry Reding "sdmmc4_dat3_paa3", 164*de1835e3SThierry Reding "sdmmc4_dat4_paa4", 165*de1835e3SThierry Reding "sdmmc4_dat5_paa5", 166*de1835e3SThierry Reding "sdmmc4_dat6_paa6", 167*de1835e3SThierry Reding "sdmmc4_dat7_paa7"; 168*de1835e3SThierry Reding nvidia,function = "sdmmc4"; 169*de1835e3SThierry Reding nvidia,pull = <TEGRA_PIN_PULL_UP>; 170*de1835e3SThierry Reding nvidia,tristate = <TEGRA_PIN_DISABLE>; 171*de1835e3SThierry Reding }; 172*de1835e3SThierry Reding }; 173*de1835e3SThierry Reding }; 174*de1835e3SThierry Reding... 175