| /linux/drivers/clk/rockchip/ |
| H A D | clk-pll.c | 52 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
58 if (rate == rate_table[i].rate) in rockchip_get_pll_settings()
74 if (req->rate >= rate_table[i].rate) { in rockchip_pll_determine_rate()
75 req->rate = rate_table[i].rate; in rockchip_pll_determine_rate()
82 req->rate = rate_table[i - 1].rate; in rockchip_pll_determine_rate()
146 struct rockchip_pll_rate_table *rate) in rockchip_rk3036_pll_get_params() argument
151 rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT) in rockchip_rk3036_pll_get_params()
153 rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT) in rockchip_rk3036_pll_get_params()
157 rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT) in rockchip_rk3036_pll_get_params()
159 rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT) in rockchip_rk3036_pll_get_params()
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| H A D | clk-cpu.c | 15 * CPU clock rate and this relation is usually specified in the hardware manual
18 * The below implementation of the CPU clock allows the rate changes of the CPU
19 * clock and the corresponding rate changes of the auxiliary clocks of the CPU
21 * for each configurable rate which is then used to program the clock hardware
22 * registers to achieve a fast co-oridinated rate change for all the CPU domain
25 * On a rate change request for the CPU clock, the rate change is propagated
29 * down in order to keep the output clock rate within the previous OPP limits.
68 struct rockchip_cpuclk *cpuclk, unsigned long rate) in rockchip_get_cpuclk_settings() argument
75 if (rate == rate_table[i].prate) in rockchip_get_cpuclk_settings()
99 const struct rockchip_cpuclk_rate_table *rate) in rockchip_cpuclk_set_dividers() argument
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| /linux/drivers/mmc/host/ |
| H A D | sdhci-of-aspeed-test.c | 8 int rate = 52000000; in aspeed_sdhci_phase_ddr52() local
11 aspeed_sdhci_phase_to_tap(NULL, rate, 0)); in aspeed_sdhci_phase_ddr52()
13 aspeed_sdhci_phase_to_tap(NULL, rate, 1)); in aspeed_sdhci_phase_ddr52()
15 aspeed_sdhci_phase_to_tap(NULL, rate, 2)); in aspeed_sdhci_phase_ddr52()
17 aspeed_sdhci_phase_to_tap(NULL, rate, 3)); in aspeed_sdhci_phase_ddr52()
19 aspeed_sdhci_phase_to_tap(NULL, rate, 4)); in aspeed_sdhci_phase_ddr52()
21 aspeed_sdhci_phase_to_tap(NULL, rate, 5)); in aspeed_sdhci_phase_ddr52()
23 aspeed_sdhci_phase_to_tap(NULL, rate, 23)); in aspeed_sdhci_phase_ddr52()
25 aspeed_sdhci_phase_to_tap(NULL, rate, 24)); in aspeed_sdhci_phase_ddr52()
27 aspeed_sdhci_phase_to_tap(NULL, rate, 25)); in aspeed_sdhci_phase_ddr52()
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| /linux/drivers/net/wireless/morsemicro/mm81x/ |
| H A D | mmrc.c | 9 * rate
15 * rate
41 * Number of attempts for each lookaround rate within at most two RC cycles
47 * Limit the number of times we try to pick a theoretically better rate to
54 * Initial and reset probability per rate in the table
57 * with no edivence and so will cause unexpected changes in the rate table
63 * rate stats
86 * The time cap on rate allocation for multiple attempts. If a single attempt
91 /* The time window for all rates in rate table */
161 /* EWMA percentage value for averaging the best rate probability variation */
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| /linux/tools/testing/selftests/tc-testing/tc-tests/actions/ |
| H A D | police.json | 20 "cmdUnderTest": "$TC actions add action police rate 1kbit burst 10k index 1",
23 "matchPattern": "action order [0-9]*: police 0x1 rate 1Kbit burst 10Kb",
46 "$TC actions add action police rate 4Mbit burst 120k index 9"
48 "cmdUnderTest": "$TC actions add action police rate 8kbit burst 24k index 9",
75 "cmdUnderTest": "$TC actions add action police rate 90kbit burst 10k mtu 1k index 98",
78 "matchPattern": "action order [0-9]*: police 0x62 rate 90Kbit burst 10Kb mtu 1Kb",
102 "cmdUnderTest": "$TC actions add action police rate 90kbit burst 10k mtu 2kb peakrate 100kbit index 3",
105 "matchPattern": "action order [0-9]*: police 0x3 rate 90Kbit burst 10Kb mtu 2Kb peakrate 100Kbit",
129 "cmdUnderTest": "$TC actions add action police rate 5kbit burst 6kb peakrate 10kbit index 9",
132 "matchPattern": "action order [0-9]*: police 0x9 rate
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| H A D | sample.json | 20 "cmdUnderTest": "$TC actions add action sample rate 10 group 1 index 2",
23 "matchPattern": "action order [0-9]+: sample rate 1/10 group 1.*index 2 ref",
47 "cmdUnderTest": "$TC actions add action sample rate 700 group 2 continue index 2",
50 "matchPattern": "action order [0-9]+: sample rate 1/700 group 2 continue.*index 2 ref",
74 "cmdUnderTest": "$TC actions add action sample rate 10000 group 11 drop index 22",
77 "matchPattern": "action order [0-9]+: sample rate 1/10000 group 11 drop.*index 22 ref",
101 "cmdUnderTest": "$TC actions add action sample rate 20000 group 72 reclassify index 100",
104 … "matchPattern": "action order [0-9]+: sample rate 1/20000 group 72 reclassify.*index 100 ref",
128 "cmdUnderTest": "$TC actions add action sample rate 20 group 2 pipe index 100",
131 "matchPattern": "action order [0-9]+: sample rate 1/20 group 2 pipe.*index 100 ref",
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| /linux/drivers/clk/ |
| H A D | clk_test.c | 31 unsigned long rate; member
41 return ctx->rate; in clk_dummy_recalc_rate()
47 /* Just return the same rate without modifying it */ in clk_dummy_determine_rate()
59 req->rate = req->max_rate; in clk_dummy_maximize_rate()
72 req->rate = req->min_rate; in clk_dummy_minimize_rate()
78 unsigned long rate, in clk_dummy_set_rate() argument
84 ctx->rate = rate; in clk_dummy_set_rate()
137 * clk_round_rate() or clk_set_rate() with a rate lower than
141 * behaviour to always pick up the closest rate higher than the
142 * requested rate. If we get something lower, it thus considers
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| H A D | clk-vt8500.c | 137 if (req->rate == 0) in vt8500_dclk_determine_rate()
140 divisor = req->best_parent_rate / req->rate; in vt8500_dclk_determine_rate()
142 /* If prate / rate would be decimal, incr the divisor */ in vt8500_dclk_determine_rate()
143 if (req->rate * divisor < req->best_parent_rate) in vt8500_dclk_determine_rate()
153 req->rate = req->best_parent_rate / divisor; in vt8500_dclk_determine_rate()
158 static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate, in vt8500_dclk_set_rate() argument
165 if (rate == 0) in vt8500_dclk_set_rate()
168 divisor = parent_rate / rate; in vt8500_dclk_set_rate()
351 static int vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate, in vt8500_find_pll_bits() argument
357 if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) { in vt8500_find_pll_bits()
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| H A D | clk-fractional-divider_test.c | 14 * requested rate.
19 unsigned long rate, parent_rate, parent_rate_before, m, n, max_n; in clk_fd_test_approximation_max_denominator() local
28 rate = 240000000; in clk_fd_test_approximation_max_denominator()
29 parent_rate = (max_n + 1) * rate; /* so that it exceeds the maximum divisor */ in clk_fd_test_approximation_max_denominator()
32 clk_fractional_divider_general_approximation(&fd->hw, rate, &parent_rate, &m, &n); in clk_fd_test_approximation_max_denominator()
43 * requested rate.
48 unsigned long rate, parent_rate, parent_rate_before, m, n, max_m; in clk_fd_test_approximation_max_numerator() local
57 rate = 240000000; in clk_fd_test_approximation_max_numerator()
58 parent_rate = rate / (max_m + 1); /* so that it exceeds the maximum numerator */ in clk_fd_test_approximation_max_numerator()
61 clk_fractional_divider_general_approximation(&fd->hw, rate, &parent_rate, &m, &n); in clk_fd_test_approximation_max_numerator()
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| /linux/drivers/clk/at91/ |
| H A D | clk-audio-pll.c | 10 * (FRAC). FRAC can output between 620 and 700MHz and only multiply the rate of
11 * its own parent. PMC and PAD can then divide the FRAC rate to best match the
12 * asked rate.
16 * rate - rate is adjustable.
17 * clk->rate = parent->rate * ((nd + 1) + (fracr / 2^22))
22 * rate - rate is adjustable.
23 * clk->rate = parent->rate / (qdpmc + 1)
28 * rate - rate is adjustable.
29 * clk->rate = parent->rate / (qdaudio * div))
216 static int clk_audio_pll_frac_compute_frac(unsigned long rate, in clk_audio_pll_frac_compute_frac() argument
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| /linux/drivers/clk/samsung/ |
| H A D | clk-pll.c | 37 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
43 if (rate == rate_table[i].rate) in samsung_get_pll_settings()
59 if (req->rate >= rate_table[i].rate) { in samsung_pll_determine_rate()
60 req->rate = rate_table[i].rate; in samsung_pll_determine_rate()
67 req->rate = rate_table[i - 1].rate; in samsung_pll_determine_rate()
231 const struct samsung_pll_rate_table *rate, u32 pll_con) in samsung_pll35xx_mp_change() argument
241 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); in samsung_pll35xx_mp_change()
248 const struct samsung_pll_rate_table *rate; in samsung_pll35xx_set_rate() local
257 /* Get required rate settings from table */ in samsung_pll35xx_set_rate()
258 rate = samsung_get_pll_settings(pll, drate); in samsung_pll35xx_set_rate()
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| /linux/drivers/clk/qcom/ |
| H A D | clk-rcg2.c | 166 * calc_rate() - Calculate rate based on m/n:d values
168 * @rate: Parent rate.
175 * Return calculated rate according to formula:
178 * rate = ----------- x ---
182 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div) in calc_rate() argument
185 rate = mult_frac(rate, 2, hid_div + 1); in calc_rate()
188 rate = mult_frac(rate, m, n); in calc_rate()
190 return rate; in calc_rate()
233 unsigned long clk_flags, rate = req->rate; in _freq_tbl_determine_rate() local
240 f = qcom_find_freq_floor(f, rate); in _freq_tbl_determine_rate()
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| /linux/net/wireless/ |
| H A D | util.c | 1377 static u32 cfg80211_calculate_bitrate_ht(struct rate_info *rate) in cfg80211_calculate_bitrate_ht() argument
1382 if (WARN_ON_ONCE(rate->mcs >= 32)) in cfg80211_calculate_bitrate_ht()
1385 modulation = rate->mcs & 7; in cfg80211_calculate_bitrate_ht()
1386 streams = (rate->mcs >> 3) + 1; in cfg80211_calculate_bitrate_ht()
1388 bitrate = (rate->bw == RATE_INFO_BW_40) ? 13500000 : 6500000; in cfg80211_calculate_bitrate_ht()
1399 if (rate->flags & RATE_INFO_FLAGS_SHORT_GI) in cfg80211_calculate_bitrate_ht()
1406 static u32 cfg80211_calculate_bitrate_dmg(struct rate_info *rate) in cfg80211_calculate_bitrate_dmg() argument
1447 if (WARN_ON_ONCE(rate->mcs >= ARRAY_SIZE(__mcs2bitrate))) in cfg80211_calculate_bitrate_dmg()
1450 return __mcs2bitrate[rate->mcs]; in cfg80211_calculate_bitrate_dmg()
1453 static u32 cfg80211_calculate_bitrate_extended_sc_dmg(struct rate_info *rate) in cfg80211_calculate_bitrate_extended_sc_dmg() argument
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| /linux/drivers/net/wireless/realtek/rtlwifi/ |
| H A D | rc.c | 9 *Finds the highest rate index we can use
11 *it to lowest rate CCK_1M, otherwise we set rate to
12 *highest rate based on wireless mode used for iwconfig
13 *show Tx rate.
24 struct ieee80211_tx_rate rate; in _rtl_rc_get_highest_rix() local
42 *this rate is no use for true rate, firmware in _rtl_rc_get_highest_rix()
43 *will control rate at all it just used for in _rtl_rc_get_highest_rix()
45 *2.in rtl_get_tcb_desc when we check rate is in _rtl_rc_get_highest_rix()
46 * 1M we will not use FW rate but user rate. in _rtl_rc_get_highest_rix()
70 ieee80211_rate_set_vht(&rate, in _rtl_rc_get_highest_rix()
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| /linux/drivers/clk/tegra/ |
| H A D | clk-tegra124-emc.c | 66 unsigned long rate, parent_rate; member
101 * so get the parent rate explicitly. in emc_recalc_rate()
112 * Rounds up unless no higher rate exists, in which case down. This way is
113 * safer since things have EMC rate floors. Also don't touch parent_rate
138 if (timing->rate < req->rate && i != t - 1) in emc_determine_rate()
141 if (timing->rate > req->max_rate) { in emc_determine_rate()
143 req->rate = tegra->timings[i - 1].rate; in emc_determine_rate()
147 if (timing->rate < req->min_rate) in emc_determine_rate()
150 req->rate = timing->rate; in emc_determine_rate()
155 req->rate = timing->rate; in emc_determine_rate()
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| /linux/tools/testing/selftests/drivers/net/hw/ |
| H A D | devlink_rate_cross_esw.py | 5 Devlink Rate Cross-eswitch Scheduling Test Suite
8 Control-plane tests for cross-eswitch TX scheduling via devlink-rate.
10 rate groups using the cross-device parent-dev attribute.
24 - cross-esw rate scheduling returns EOPNOTSUPP.
107 # --- Rate operation helpers ---
111 """Creates rate node."""
115 "rate-node-name": node_name,
127 """Gets rate node."""
131 "rate-node-name": node_name,
137 """Gets rate leaf (VF)."""
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| /linux/drivers/clk/ti/ |
| H A D | clkt_dpll.c | 25 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
33 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
35 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
124 * @new_rate: pointer to storage for the resulting rounded rate
125 * @target_rate: the desired DPLL rate
126 * @parent_rate: the DPLL's parent clock rate
129 * resulting rate will not be higher than the target_rate, and that
152 * The new rate must be <= the target rate to avoid programming in _dpll_test_mult()
153 * a rate that is impossible for the hardware to handle in _dpll_test_mult()
225 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
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| H A D | dpll44xx.c | 34 /* Static rate multiplier for OMAP4 REGM4XEN clocks */
104 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
105 * @hw: pointer to the clock to compute the rate for
106 * @parent_rate: clock rate of the DPLL parent
108 * Compute the output rate for the OMAP4 DPLL represented by @clk.
110 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
118 unsigned long rate; in omap4_dpll_regm4xen_recalc() local
126 rate = omap2_get_dpll_rate(clk); in omap4_dpll_regm4xen_recalc()
131 rate *= OMAP4430_REGM4XEN_MULT; in omap4_dpll_regm4xen_recalc()
133 return rate; in omap4_dpll_regm4xen_recalc()
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| /linux/drivers/clk/imx/ |
| H A D | clk-pll14xx.c | 98 struct clk_pll14xx *pll, unsigned long rate) in imx_get_pll_settings() argument
104 if (rate == rate_table[i].rate) in imx_get_pll_settings()
125 unsigned long rate, unsigned long prate) in pll1443x_calc_kdiv() argument
129 /* calc kdiv = round(rate * pdiv * 65536 * 2^sdiv / prate) - (mdiv * 65536) */ in pll1443x_calc_kdiv()
130 kdiv = ((rate * ((pdiv * 65536) << sdiv) + prate / 2) / prate) - (mdiv * 65536); in pll1443x_calc_kdiv()
135 static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rate, in imx_pll14xx_calc_settings() argument
156 /* First try if we can get the desired rate from one of the static entries */ in imx_pll14xx_calc_settings()
157 tt = imx_get_pll_settings(pll, rate); in imx_pll14xx_calc_settings()
160 clk_hw_get_name(&pll->hw), prate, rate); in imx_pll14xx_calc_settings()
161 t->rate = tt->rate; in imx_pll14xx_calc_settings()
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| H A D | clk-pllv3.c | 40 * @ref_clock: reference clock rate
125 req->rate = (req->rate >= parent_rate * 22) ? parent_rate * 22 : parent_rate * 20; in clk_pllv3_determine_rate()
130 static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, in clk_pllv3_set_rate() argument
136 if (rate == parent_rate * 22) in clk_pllv3_set_rate()
138 else if (rate == parent_rate * 20) in clk_pllv3_set_rate()
177 if (req->rate > max_rate) in clk_pllv3_sys_determine_rate()
178 req->rate = max_rate; in clk_pllv3_sys_determine_rate()
179 else if (req->rate < min_rate) in clk_pllv3_sys_determine_rate()
180 req->rate = min_rate; in clk_pllv3_sys_determine_rate()
181 div = req->rate * 2 / parent_rate; in clk_pllv3_sys_determine_rate()
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| /linux/sound/soc/mediatek/mt8186/ |
| H A D | mt8186-afe-control.c | 75 unsigned int mt8186_general_rate_transform(struct device *dev, unsigned int rate) in mt8186_general_rate_transform() argument
77 switch (rate) { in mt8186_general_rate_transform()
111 dev_err(dev, "%s(), rate %u invalid, use %d!!!\n", in mt8186_general_rate_transform()
112 __func__, rate, MTK_AFE_RATE_48K); in mt8186_general_rate_transform()
118 static unsigned int tdm_rate_transform(struct device *dev, unsigned int rate) in tdm_rate_transform() argument
120 switch (rate) { in tdm_rate_transform()
158 dev_err(dev, "%s(), rate %u invalid, use %d!!!\n", in tdm_rate_transform()
159 __func__, rate, MTK_AFE_TDM_RATE_48K); in tdm_rate_transform()
165 static unsigned int pcm_rate_transform(struct device *dev, unsigned int rate) in pcm_rate_transform() argument
167 switch (rate) { in pcm_rate_transform()
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| /linux/arch/arm/mach-omap2/ |
| H A D | clkt2xxx_virt_prcm_set.c | 16 * code. However, some notion of "rate set" is probably still necessary
17 * for OMAP2xxx at least. Rate sets should be generalized so they can be
19 * has in the past expressed a preference to use rate sets for OPP changes,
48 * sys_ck_rate: the rate of the external high-frequency clock
58 * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
67 * Look for a rate equal or less than the target rate given a configuration set.
90 if (ptr->mpu_speed <= req->rate) in omap2_determine_rate_to_table()
93 req->rate = highest_rate; in omap2_determine_rate_to_table()
98 /* Sets basic clocks based on the specified rate */
99 static int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate, in omap2_select_table_rate() argument
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| /linux/arch/arm/mach-omap1/ |
| H A D | clock.h | 40 #define CK_1710 (1 << 4) /* 1710 extra for rate selection */
66 * @rate: current clock rate
68 * @recalc: fn ptr that returns the clock's current rate
69 * @set_rate: fn ptr that can change the clock's current rate
70 * @round_rate: fn ptr that can round the clock's current rate
73 * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
75 * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
80 unsigned long rate; member
82 unsigned long (*recalc)(struct omap1_clk *clk, unsigned long rate);
83 int (*set_rate)(struct omap1_clk *clk, unsigned long rate,
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| /linux/drivers/clk/actions/ |
| H A D | owl-factor.c | 44 unsigned long rate, unsigned long parent_rate) in _get_table_val() argument
54 if ((unsigned long)calc_rate <= rate) { in _get_table_val()
67 struct clk_hw *hw, unsigned long rate, in owl_clk_val_best() argument
75 if (!rate) in owl_clk_val_best()
76 rate = 1; in owl_clk_val_best()
80 bestval = _get_table_val(clkt, rate, parent_rate); in owl_clk_val_best()
85 try_parent_rate = rate * clkt->div / clkt->mul; in owl_clk_val_best()
92 * It's the most ideal case if the requested rate can be in owl_clk_val_best()
94 * parent rate, so return the divider immediately. in owl_clk_val_best()
103 if (cur_rate <= rate && cur_rate > best) { in owl_clk_val_best()
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| /linux/drivers/clk/mmp/ |
| H A D | clk-frac.c | 28 u64 rate = 0, prev_rate; in clk_factor_determine_rate() local
35 prev_rate = rate; in clk_factor_determine_rate()
36 rate = (u64)(req->best_parent_rate) * d->denominator; in clk_factor_determine_rate()
37 do_div(rate, d->numerator * factor->masks->factor); in clk_factor_determine_rate()
38 if (rate > req->rate) in clk_factor_determine_rate()
43 req->rate = rate; in clk_factor_determine_rate()
44 else if ((req->rate - prev_rate) > (rate - req->rate)) in clk_factor_determine_rate()
45 req->rate = rate; in clk_factor_determine_rate()
47 req->rate = prev_rate; in clk_factor_determine_rate()
59 u64 rate; in clk_factor_recalc_rate() local
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