Lines Matching full:rate
166 * calc_rate() - Calculate rate based on m/n:d values
168 * @rate: Parent rate.
175 * Return calculated rate according to formula:
178 * rate = ----------- x ---
182 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
185 rate = mult_frac(rate, 2, hid_div + 1);
188 rate = mult_frac(rate, m, n);
190 return rate;
233 unsigned long clk_flags, rate = req->rate;
240 f = qcom_find_freq_floor(f, rate);
243 f = qcom_find_freq(f, rate);
262 rate = f->freq;
264 if (!rate)
265 rate = req->rate;
266 rate /= 2;
267 rate *= f->pre_div + 1;
271 u64 tmp = rate;
274 rate = tmp;
277 rate = clk_hw_get_rate(p);
280 req->best_parent_rate = rate;
281 req->rate = f->freq;
294 unsigned long parent_rate, rate;
304 /* Search in each provided config the one that is near the wanted rate */
315 rate = calc_rate(parent_rate, conf->n, conf->m, conf->n, conf->pre_div);
317 if (rate == req_rate) {
322 rate_diff = abs_diff(req_rate, rate);
334 WARN(1, "%s: can't find a configuration for rate %lu\n",
346 unsigned long clk_flags, rate = req->rate;
352 f = qcom_find_freq_multi(f, rate);
356 conf = __clk_rcg2_select_conf(hw, f, rate);
369 rate = f->freq;
371 if (!rate)
372 rate = req->rate;
373 rate /= 2;
374 rate *= conf->pre_div + 1;
378 u64 tmp = rate;
382 rate = tmp;
385 rate = clk_hw_get_rate(p);
389 req->best_parent_rate = rate;
390 req->rate = f->freq;
434 static void clk_rcg2_calc_mnd(u64 parent_rate, u64 rate, struct freq_tbl *f,
442 rates_gcd = gcd(parent_rate, rate);
443 m = div64_u64(rate, rates_gcd);
496 clk_rcg2_calc_mnd(parent_rate, req->rate, f, mnd_max, hid_max / 2);
498 req->rate = calc_rate(parent_rate, f->m, f->n, f->n, f->pre_div);
620 static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
628 f = qcom_find_freq_floor(rcg->freq_tbl, rate);
631 f = qcom_find_freq(rcg->freq_tbl, rate);
643 static int __clk_rcg2_fm_set_rate(struct clk_hw *hw, unsigned long rate)
650 f = qcom_find_freq_multi(rcg->freq_multi_tbl, rate);
654 conf = __clk_rcg2_select_conf(hw, f, rate);
667 static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
670 return __clk_rcg2_set_rate(hw, rate, CEIL);
673 static int clk_rcg2_set_gp_rate(struct clk_hw *hw, unsigned long rate,
682 clk_rcg2_calc_mnd(parent_rate, rate, f, mnd_max, hid_max / 2);
689 static int clk_rcg2_set_floor_rate(struct clk_hw *hw, unsigned long rate,
692 return __clk_rcg2_set_rate(hw, rate, FLOOR);
695 static int clk_rcg2_fm_set_rate(struct clk_hw *hw, unsigned long rate,
698 return __clk_rcg2_fm_set_rate(hw, rate);
702 unsigned long rate, unsigned long parent_rate, u8 index)
704 return __clk_rcg2_set_rate(hw, rate, CEIL);
708 unsigned long rate, unsigned long parent_rate, u8 index)
710 return __clk_rcg2_set_rate(hw, rate, FLOOR);
714 unsigned long rate, unsigned long parent_rate, u8 index)
716 return __clk_rcg2_fm_set_rate(hw, rate);
866 static const struct frac_entry frac_table_675m[] = { /* link rate of 270M */
877 static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */
888 static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
906 request = rate;
928 unsigned long rate, unsigned long parent_rate, u8 index)
931 return clk_edp_pixel_set_rate(hw, rate, parent_rate);
956 request = req->rate;
968 req->rate = calc_rate(req->best_parent_rate,
998 if (req->rate == 0)
1002 req->best_parent_rate = parent_rate = clk_hw_round_rate(p, req->rate);
1004 div = DIV_ROUND_UP((2 * parent_rate), req->rate) - 1;
1007 req->rate = calc_rate(parent_rate, 0, 0, 0, div);
1012 static int clk_byte_set_rate(struct clk_hw *hw, unsigned long rate,
1020 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
1029 unsigned long rate, unsigned long parent_rate, u8 index)
1032 return clk_byte_set_rate(hw, rate, parent_rate);
1053 unsigned long rate = req->rate;
1055 if (rate == 0)
1059 req->best_parent_rate = parent_rate = clk_hw_round_rate(p, rate);
1061 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
1064 req->rate = calc_rate(parent_rate, 0, 0, 0, div);
1069 static int clk_byte2_set_rate(struct clk_hw *hw, unsigned long rate,
1079 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
1099 unsigned long rate, unsigned long parent_rate, u8 index)
1102 return clk_byte2_set_rate(hw, rate, parent_rate);
1133 request = (req->rate * frac->den) / frac->num;
1141 req->rate = (src_rate * frac->num) / frac->den;
1148 static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
1171 request = (rate * frac->den) / frac->num;
1190 static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
1193 return clk_pixel_set_rate(hw, rate, parent_rate);
1229 if (req->rate == clk_hw_get_rate(xo)) {
1237 parent_req.rate = req->rate * mux_div;
1239 /* This has to be a fixed rate PLL */
1242 if (parent_req.rate == p0_rate) {
1243 req->rate = req->best_parent_rate = p0_rate;
1249 /* Are we going back to a previously used rate? */
1250 if (clk_hw_get_rate(p2) == parent_req.rate)
1273 req->rate = req->best_parent_rate = parent_req.rate;
1274 req->rate /= mux_div;
1279 static int clk_gfx3d_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
1299 static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate,
1369 static int __clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate,
1378 f = qcom_find_freq_floor(rcg->freq_tbl, rate);
1381 f = qcom_find_freq(rcg->freq_tbl, rate);
1398 static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate,
1401 return __clk_rcg2_shared_set_rate(hw, rate, parent_rate, CEIL);
1405 unsigned long rate, unsigned long parent_rate, u8 index)
1407 return __clk_rcg2_shared_set_rate(hw, rate, parent_rate, CEIL);
1410 static int clk_rcg2_shared_set_floor_rate(struct clk_hw *hw, unsigned long rate,
1413 return __clk_rcg2_shared_set_rate(hw, rate, parent_rate, FLOOR);
1417 unsigned long rate, unsigned long parent_rate, u8 index)
1419 return __clk_rcg2_shared_set_rate(hw, rate, parent_rate, FLOOR);
1435 /* Write back the stored configuration corresponding to current rate */
1753 * Rate changes with consumer writing a register in
1779 static int clk_rcg2_dp_set_rate(struct clk_hw *hw, unsigned long rate,
1789 rational_best_approximation(parent_rate, rate,
1824 unsigned long rate, unsigned long parent_rate, u8 index)
1826 return clk_rcg2_dp_set_rate(hw, rate, parent_rate);
1836 /* Parent rate is a fixed phy link rate */
1837 rational_best_approximation(req->best_parent_rate, req->rate,
1846 req->rate = tmp;