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Searched +full:r9a06g032 +full:- +full:sysctrl (Results 1 – 14 of 14) sorted by relevance

/linux/arch/arm/boot/dts/renesas/
H A Dr9a06g032.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
13 compatible = "renesas,r9a06g032";
14 #address-cells = <1>;
15 #size-cells = <1>;
16 interrupt-parent = <&gic>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,r9a06g032-sysctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,r9a06g032-sysctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/N1D (R9A06G032) System Controller
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
15 const: renesas,r9a06g032-sysctrl
23 - description: External 40 MHz crystal
24 - description: Optional external 32.768 kHz crystal
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/linux/Documentation/devicetree/bindings/mtd/
H A Drenesas-nandc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/renesas-nandc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Gen3 & RZ/N1x NAND flash controller
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: nand-controller.yaml
18 - items:
19 - enum:
20 - renesas,r9a06g032-nandc
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/linux/Documentation/devicetree/bindings/usb/
H A Drenesas,rzn1-usbf.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/renesas,rzn1-usbf.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Herve Codina <herve.codina@bootlin.com>
19 - enum:
20 - renesas,r9a06g032-usbf
21 - const: renesas,rzn1-usbf
28 - description: Internal bus clock (AHB) for Function
29 - description: Internal bus clock (AHB) for Power Management
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/linux/Documentation/devicetree/bindings/rtc/
H A Drenesas,rzn1-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/renesas,rzn1-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/N1 SoCs Real-Time Clock
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: rtc.yaml#
18 - enum:
19 - renesas,r9a06g032-rtc
20 - const: renesas,rzn1-rtc
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/linux/Documentation/devicetree/bindings/iio/adc/
H A Drenesas,rzn1-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/renesas,rzn1-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
20 - const: renesas,r9a06g032-adc # RZ/N1D
21 - const: renesas,rzn1-adc
28 - description: APB internal bus clock
29 - description: ADC clock
31 clock-names:
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/linux/Documentation/devicetree/bindings/net/dsa/
H A Drenesas,rzn1-a5psw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Clément Léger <clement.leger@bootlin.com>
17 - $ref: dsa.yaml#/$defs/ethernet-ports
22 - enum:
23 - renesas,r9a06g032-a5psw
24 - const: renesas,rzn1-a5psw
31 - description: Device Level Ring (DLR) interrupt
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/linux/Documentation/devicetree/bindings/watchdog/
H A Drenesas,rzn1-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/renesas,rzn1-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfram Sang <wsa+renesas@sang-engineering.com>
15 - const: renesas,r9a06g032-wdt # RZ/N1D
16 - const: renesas,rzn1-wdt # RZ/N1
27 timeout-sec: true
30 - compatible
31 - reg
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/linux/Documentation/devicetree/bindings/net/can/
H A Dnxp,sja1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - const: renesas,r9a06g032-sja1000 # RZ/N1D
20 - const: renesas,rzn1-sja1000 # RZ/N1
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Drenesas,rzn1-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 - const: renesas,r9a06g032-pinctrl # RZ/N1D
17 - const: renesas,rzn1-pinctrl # Generic RZ/N1
21 - description: GPIO Multiplexing Level1 Register Block
22 - description: GPIO Multiplexing Level2 Register Block
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/linux/drivers/soc/renesas/
H A Dr9a06g032-smp.c1 // SPDX-License-Identifier: GPL-2.0
3 * R9A06G032 Second CA7 enabler.
8 * Derived from actions,s500-smp
18 * writing an address into the BOOTADDR register of sysctrl.
20 * So the default value of the "cpu-release-addr" corresponds to BOOTADDR...
25 * So for NONSEC mode, the bootloader re-parks the second CPU into a pen
26 * in SRAM, and changes the "cpu-release-addr" of linux's DT to a SRAM address,
39 return -ENODEV; in r9a06g032_smp_boot_secondary()
54 int ret = -EINVAL, dns; in r9a06g032_smp_prepare_cpus()
67 if (of_find_property(dn, "cpu-release-addr", &dns)) { in r9a06g032_smp_prepare_cpus()
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/linux/include/dt-bindings/clock/
H A Dr9a06g032-sysctrl.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * R9A06G032 sysctrl IDs
/linux/drivers/dma/dw/
H A Drzn1-dmamux.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2022 Schneider-Electric
13 #include <linux/soc/renesas/r9a06g032-sysctrl.h>
34 dev_dbg(dev, "Unmapping DMAMUX request %u\n", map->req_idx); in rzn1_dmamux_free()
36 clear_bit(map->req_idx, dmamux->used_chans); in rzn1_dmamux_free()
44 struct platform_device *pdev = of_find_device_by_node(ofdma->of_node); in rzn1_dmamux_route_allocate()
51 if (dma_spec->args_count != RNZ1_DMAMUX_NCELLS) { in rzn1_dmamux_route_allocate()
52 ret = -EINVAL; in rzn1_dmamux_route_allocate()
58 ret = -ENOMEM; in rzn1_dmamux_route_allocate()
62 chan = dma_spec->args[0]; in rzn1_dmamux_route_allocate()
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/linux/drivers/clk/renesas/
H A Dr9a06g032-clocks.c1 // SPDX-License-Identifier: GPL-2.0
3 * R9A06G032 clock driver
11 #include <linux/clk-provider.h>
25 #include <linux/soc/renesas/r9a06g032-sysctrl.h>
27 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
42 * struct regbit - describe one bit in a register
44 * expressed in units of 32-bit words (not bytes),
52 * Since registers are aligned on 32-bit boundaries, the
53 * offset will be specified in 32-bit words rather than bytes.
57 * offset from bytes to 32-bit words.
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