1*7416d441SMichel Pollet // SPDX-License-Identifier: GPL-2.0
2*7416d441SMichel Pollet /*
3*7416d441SMichel Pollet * R9A06G032 Second CA7 enabler.
4*7416d441SMichel Pollet *
5*7416d441SMichel Pollet * Copyright (C) 2018 Renesas Electronics Europe Limited
6*7416d441SMichel Pollet *
7*7416d441SMichel Pollet * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
8*7416d441SMichel Pollet * Derived from actions,s500-smp
9*7416d441SMichel Pollet */
10*7416d441SMichel Pollet
11*7416d441SMichel Pollet #include <linux/io.h>
12*7416d441SMichel Pollet #include <linux/of.h>
13*7416d441SMichel Pollet #include <linux/of_address.h>
14*7416d441SMichel Pollet #include <linux/smp.h>
15*7416d441SMichel Pollet
16*7416d441SMichel Pollet /*
17*7416d441SMichel Pollet * The second CPU is parked in ROM at boot time. It requires waking it after
18*7416d441SMichel Pollet * writing an address into the BOOTADDR register of sysctrl.
19*7416d441SMichel Pollet *
20*7416d441SMichel Pollet * So the default value of the "cpu-release-addr" corresponds to BOOTADDR...
21*7416d441SMichel Pollet *
22*7416d441SMichel Pollet * *However* the BOOTADDR register is not available when the kernel
23*7416d441SMichel Pollet * starts in NONSEC mode.
24*7416d441SMichel Pollet *
25*7416d441SMichel Pollet * So for NONSEC mode, the bootloader re-parks the second CPU into a pen
26*7416d441SMichel Pollet * in SRAM, and changes the "cpu-release-addr" of linux's DT to a SRAM address,
27*7416d441SMichel Pollet * which is not restricted.
28*7416d441SMichel Pollet */
29*7416d441SMichel Pollet
30*7416d441SMichel Pollet static void __iomem *cpu_bootaddr;
31*7416d441SMichel Pollet
32*7416d441SMichel Pollet static DEFINE_SPINLOCK(cpu_lock);
33*7416d441SMichel Pollet
34*7416d441SMichel Pollet static int
r9a06g032_smp_boot_secondary(unsigned int cpu,struct task_struct * idle)35*7416d441SMichel Pollet r9a06g032_smp_boot_secondary(unsigned int cpu,
36*7416d441SMichel Pollet struct task_struct *idle)
37*7416d441SMichel Pollet {
38*7416d441SMichel Pollet if (!cpu_bootaddr)
39*7416d441SMichel Pollet return -ENODEV;
40*7416d441SMichel Pollet
41*7416d441SMichel Pollet spin_lock(&cpu_lock);
42*7416d441SMichel Pollet
43*7416d441SMichel Pollet writel(__pa_symbol(secondary_startup), cpu_bootaddr);
44*7416d441SMichel Pollet arch_send_wakeup_ipi_mask(cpumask_of(cpu));
45*7416d441SMichel Pollet
46*7416d441SMichel Pollet spin_unlock(&cpu_lock);
47*7416d441SMichel Pollet
48*7416d441SMichel Pollet return 0;
49*7416d441SMichel Pollet }
50*7416d441SMichel Pollet
r9a06g032_smp_prepare_cpus(unsigned int max_cpus)51*7416d441SMichel Pollet static void __init r9a06g032_smp_prepare_cpus(unsigned int max_cpus)
52*7416d441SMichel Pollet {
53*7416d441SMichel Pollet struct device_node *dn;
54*7416d441SMichel Pollet int ret = -EINVAL, dns;
55*7416d441SMichel Pollet u32 bootaddr;
56*7416d441SMichel Pollet
57*7416d441SMichel Pollet dn = of_get_cpu_node(1, NULL);
58*7416d441SMichel Pollet if (!dn) {
59*7416d441SMichel Pollet pr_err("CPU#1: missing device tree node\n");
60*7416d441SMichel Pollet return;
61*7416d441SMichel Pollet }
62*7416d441SMichel Pollet /*
63*7416d441SMichel Pollet * Determine the address from which the CPU is polling.
64*7416d441SMichel Pollet * The bootloader *does* change this property.
65*7416d441SMichel Pollet * Note: The property can be either 64 or 32 bits, so handle both cases
66*7416d441SMichel Pollet */
67*7416d441SMichel Pollet if (of_find_property(dn, "cpu-release-addr", &dns)) {
68*7416d441SMichel Pollet if (dns == sizeof(u64)) {
69*7416d441SMichel Pollet u64 temp;
70*7416d441SMichel Pollet
71*7416d441SMichel Pollet ret = of_property_read_u64(dn,
72*7416d441SMichel Pollet "cpu-release-addr", &temp);
73*7416d441SMichel Pollet bootaddr = temp;
74*7416d441SMichel Pollet } else {
75*7416d441SMichel Pollet ret = of_property_read_u32(dn,
76*7416d441SMichel Pollet "cpu-release-addr",
77*7416d441SMichel Pollet &bootaddr);
78*7416d441SMichel Pollet }
79*7416d441SMichel Pollet }
80*7416d441SMichel Pollet of_node_put(dn);
81*7416d441SMichel Pollet if (ret) {
82*7416d441SMichel Pollet pr_err("CPU#1: invalid cpu-release-addr property\n");
83*7416d441SMichel Pollet return;
84*7416d441SMichel Pollet }
85*7416d441SMichel Pollet pr_info("CPU#1: cpu-release-addr %08x\n", bootaddr);
86*7416d441SMichel Pollet
87*7416d441SMichel Pollet cpu_bootaddr = ioremap(bootaddr, sizeof(bootaddr));
88*7416d441SMichel Pollet }
89*7416d441SMichel Pollet
90*7416d441SMichel Pollet static const struct smp_operations r9a06g032_smp_ops __initconst = {
91*7416d441SMichel Pollet .smp_prepare_cpus = r9a06g032_smp_prepare_cpus,
92*7416d441SMichel Pollet .smp_boot_secondary = r9a06g032_smp_boot_secondary,
93*7416d441SMichel Pollet };
94*7416d441SMichel Pollet
95*7416d441SMichel Pollet CPU_METHOD_OF_DECLARE(r9a06g032_smp,
96*7416d441SMichel Pollet "renesas,r9a06g032-smp", &r9a06g032_smp_ops);
97