Lines Matching +full:r9a06g032 +full:- +full:sysctrl
1 // SPDX-License-Identifier: GPL-2.0
3 * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
13 compatible = "renesas,r9a06g032";
14 #address-cells = <1>;
15 #size-cells = <1>;
16 interrupt-parent = <&gic>;
19 #address-cells = <1>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-a7";
26 clocks = <&sysctrl R9A06G032_CLK_A7MP>;
31 compatible = "arm,cortex-a7";
33 clocks = <&sysctrl R9A06G032_CLK_A7MP>;
34 enable-method = "renesas,r9a06g032-smp";
35 cpu-release-addr = <0 0x4000c204>;
40 #clock-cells = <0>;
41 compatible = "fixed-clock";
42 clock-frequency = <0>;
46 #clock-cells = <0>;
47 compatible = "fixed-clock";
48 clock-frequency = <40000000>;
52 #clock-cells = <0>;
53 compatible = "fixed-clock";
54 clock-frequency = <0>;
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <0>;
64 compatible = "simple-bus";
65 #address-cells = <1>;
66 #size-cells = <1>;
70 compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
75 interrupt-names = "alarm", "timer", "pps";
76 clocks = <&sysctrl R9A06G032_HCLK_RTC>, <&ext_rtc_clk>;
77 clock-names = "hclk", "xtal";
78 power-domains = <&sysctrl>;
83 compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
86 clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
91 compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
94 clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
98 sysctrl: system-controller@4000c000 { label
99 compatible = "renesas,r9a06g032-sysctrl";
102 #clock-cells = <1>;
103 #power-domain-cells = <0>;
107 clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
108 #address-cells = <1>;
109 #size-cells = <1>;
111 dmamux: dma-router@a0 {
112 compatible = "renesas,rzn1-dmamux";
114 #dma-cells = <6>;
115 dma-requests = <32>;
116 dma-masters = <&dma0 &dma1>;
121 compatible = "renesas,r9a06g032-usbf", "renesas,rzn1-usbf";
125 clocks = <&sysctrl R9A06G032_HCLK_USBF>,
126 <&sysctrl R9A06G032_HCLK_USBPM>;
127 clock-names = "hclkf", "hclkpm";
128 power-domains = <&sysctrl>;
133 compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
135 clocks = <&sysctrl R9A06G032_HCLK_USBH>,
136 <&sysctrl R9A06G032_HCLK_USBPM>,
137 <&sysctrl R9A06G032_CLK_PCI_USB>;
138 clock-names = "hclkh", "hclkpm", "pciclk";
139 power-domains = <&sysctrl>;
145 bus-range = <0 0>;
146 #address-cells = <3>;
147 #size-cells = <2>;
148 #interrupt-cells = <1>;
152 * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit)
154 dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>;
155 interrupt-map-mask = <0xf800 0 0 0x7>;
156 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
163 phy-names = "usb";
169 phy-names = "usb";
174 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
177 reg-shift = <2>;
178 reg-io-width = <4>;
179 clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
180 clock-names = "baudclk", "apb_pclk";
185 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
188 reg-shift = <2>;
189 reg-io-width = <4>;
190 clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>;
191 clock-names = "baudclk", "apb_pclk";
196 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
199 reg-shift = <2>;
200 reg-io-width = <4>;
201 clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>;
202 clock-names = "baudclk", "apb_pclk";
207 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
210 reg-shift = <2>;
211 reg-io-width = <4>;
212 clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
213 clock-names = "baudclk", "apb_pclk";
215 dma-names = "tx", "rx";
220 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
223 reg-shift = <2>;
224 reg-io-width = <4>;
225 clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
226 clock-names = "baudclk", "apb_pclk";
228 dma-names = "tx", "rx";
233 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
236 reg-shift = <2>;
237 reg-io-width = <4>;
238 clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
239 clock-names = "baudclk", "apb_pclk";
241 dma-names = "tx", "rx";
246 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
249 reg-shift = <2>;
250 reg-io-width = <4>;
251 clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
252 clock-names = "baudclk", "apb_pclk";
254 dma-names = "tx", "rx";
259 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
262 reg-shift = <2>;
263 reg-io-width = <4>;
264 clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
265 clock-names = "baudclk", "apb_pclk";
267 dma-names = "tx", "rx";
272 compatible = "renesas,r9a06g032-i2c", "renesas,rzn1-i2c", "snps,designware-i2c";
275 clocks = <&sysctrl R9A06G032_HCLK_I2C0>, <&sysctrl R9A06G032_CLK_I2C0>;
276 clock-names = "ref", "pclk";
277 #address-cells = <1>;
278 #size-cells = <0>;
283 compatible = "renesas,r9a06g032-i2c", "renesas,rzn1-i2c", "snps,designware-i2c";
286 clocks = <&sysctrl R9A06G032_HCLK_I2C1>, <&sysctrl R9A06G032_CLK_I2C1>;
287 clock-names = "ref", "pclk";
288 #address-cells = <1>;
289 #size-cells = <0>;
294 compatible = "renesas,r9a06g032-adc", "renesas,rzn1-adc";
296 clocks = <&sysctrl R9A06G032_HCLK_ADC>, <&sysctrl R9A06G032_CLK_ADC>;
297 clock-names = "pclk", "adc";
298 power-domains = <&sysctrl>;
299 #io-channel-cells = <1>;
304 compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
306 clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
307 clock-names = "bus";
312 compatible = "renesas,r9a06g032-sdhci", "renesas,rzn1-sdhci", "arasan,sdhci-8.9a";
316 interrupt-names = "int", "wakeup";
317 clocks = <&sysctrl R9A06G032_CLK_SDIO0>, <&sysctrl R9A06G032_HCLK_SDIO0>;
318 clock-names = "clk_xin", "clk_ahb";
319 no-1-8-v;
324 compatible = "renesas,r9a06g032-sdhci", "renesas,rzn1-sdhci", "arasan,sdhci-8.9a";
328 interrupt-names = "int", "wakeup";
329 clocks = <&sysctrl R9A06G032_CLK_SDIO1>, <&sysctrl R9A06G032_HCLK_SDIO1>;
330 clock-names = "clk_xin", "clk_ahb";
331 no-1-8-v;
335 nand_controller: nand-controller@40102000 {
336 compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc";
339 clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>;
340 clock-names = "hclk", "eclk";
341 power-domains = <&sysctrl>;
342 #address-cells = <1>;
343 #size-cells = <0>;
347 dma0: dma-controller@40104000 {
348 compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
351 clock-names = "hclk";
352 clocks = <&sysctrl R9A06G032_HCLK_DMA0>;
353 dma-channels = <8>;
354 dma-requests = <16>;
355 dma-masters = <1>;
356 #dma-cells = <3>;
358 data-width = <8>;
361 dma1: dma-controller@40105000 {
362 compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
365 clock-names = "hclk";
366 clocks = <&sysctrl R9A06G032_HCLK_DMA1>;
367 dma-channels = <8>;
368 dma-requests = <16>;
369 dma-masters = <1>;
370 #dma-cells = <3>;
372 data-width = <8>;
376 compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac";
381 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
382 clocks = <&sysctrl R9A06G032_HCLK_GMAC0>;
383 clock-names = "stmmaceth";
384 power-domains = <&sysctrl>;
385 snps,multicast-filter-bins = <256>;
386 snps,perfect-filter-entries = <128>;
387 tx-fifo-depth = <2048>;
388 rx-fifo-depth = <4096>;
389 pcs-handle = <&mii_conv1>;
394 compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac";
399 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
400 clocks = <&sysctrl R9A06G032_HCLK_GMAC1>;
401 clock-names = "stmmaceth";
402 power-domains = <&sysctrl>;
403 snps,multicast-filter-bins = <256>;
404 snps,perfect-filter-entries = <128>;
405 tx-fifo-depth = <2048>;
406 rx-fifo-depth = <4096>;
410 eth_miic: eth-miic@44030000 {
411 compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic";
412 #address-cells = <1>;
413 #size-cells = <0>;
415 clocks = <&sysctrl R9A06G032_CLK_MII_REF>,
416 <&sysctrl R9A06G032_CLK_RGMII_REF>,
417 <&sysctrl R9A06G032_CLK_RMII_REF>,
418 <&sysctrl R9A06G032_HCLK_SWITCH_RG>;
419 clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";
420 power-domains = <&sysctrl>;
423 mii_conv1: mii-conv@1 {
428 mii_conv2: mii-conv@2 {
433 mii_conv3: mii-conv@3 {
438 mii_conv4: mii-conv@4 {
443 mii_conv5: mii-conv@5 {
450 compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw";
452 clocks = <&sysctrl R9A06G032_HCLK_SWITCH>,
453 <&sysctrl R9A06G032_CLK_SWITCH>;
454 clock-names = "hclk", "clk";
455 power-domains = <&sysctrl>;
458 ethernet-ports {
459 #address-cells = <1>;
460 #size-cells = <0>;
464 pcs-handle = <&mii_conv5>;
470 pcs-handle = <&mii_conv4>;
476 pcs-handle = <&mii_conv3>;
482 pcs-handle = <&mii_conv2>;
490 phy-mode = "internal";
492 fixed-link {
494 full-duplex;
500 gic: interrupt-controller@44101000 {
501 compatible = "arm,gic-400", "arm,cortex-a7-gic";
502 interrupt-controller;
503 #interrupt-cells = <3>;
513 compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";
515 reg-io-width = <4>;
517 clocks = <&sysctrl R9A06G032_HCLK_CAN0>;
518 power-domains = <&sysctrl>;
523 compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";
525 reg-io-width = <4>;
527 clocks = <&sysctrl R9A06G032_HCLK_CAN1>;
528 power-domains = <&sysctrl>;
534 compatible = "arm,armv7-timer";
535 arm,cpu-registers-not-fw-configured;
536 always-on;
542 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
545 usbphy: usb-phy {
546 #phy-cells = <0>;
547 compatible = "usb-nop-xceiv";