Searched +full:qilai +full:- +full:plmt (Results 1 – 2 of 2) sorted by relevance
| /linux/Documentation/devicetree/bindings/timer/ |
| H A D | andestech,plmt0.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Andes machine-level timer
10 The Andes machine-level timer device (PLMT0) provides machine-level timer
11 functionality for a set of HARTs on a RISC-V platform. It has a single
12 fixed-frequency monotonic time counter (MTIME) register and a time compare
17 - Ben Zong-You Xie <ben717@andestech.com>
22 - enum:
23 - andestech,qilai-plmt
[all …]
|
| /linux/arch/riscv/boot/dts/andes/ |
| H A D | qilai.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 timebase-frequency = <62500000>;
23 riscv,isa-base = "rv64i";
24 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
[all …]
|