Lines Matching +full:qilai +full:- +full:plmt
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 timebase-frequency = <62500000>;
23 riscv,isa-base = "rv64i";
24 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
27 mmu-type = "riscv,sv39";
28 clock-frequency = <100000000>;
29 i-cache-size = <0x8000>;
30 i-cache-sets = <256>;
31 i-cache-line-size = <64>;
32 d-cache-size = <0x8000>;
33 d-cache-sets = <128>;
34 d-cache-line-size = <64>;
35 next-level-cache = <&l2_cache>;
37 cpu0_intc: interrupt-controller {
38 compatible = "andestech,cpu-intc", "riscv,cpu-intc";
39 #interrupt-cells = <1>;
40 interrupt-controller;
48 riscv,isa-base = "rv64i";
49 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
52 mmu-type = "riscv,sv39";
53 clock-frequency = <100000000>;
54 i-cache-size = <0x8000>;
55 i-cache-sets = <256>;
56 i-cache-line-size = <64>;
57 d-cache-size = <0x8000>;
58 d-cache-sets = <128>;
59 d-cache-line-size = <64>;
60 next-level-cache = <&l2_cache>;
62 cpu1_intc: interrupt-controller {
63 compatible = "andestech,cpu-intc",
64 "riscv,cpu-intc";
65 #interrupt-cells = <1>;
66 interrupt-controller;
74 riscv,isa-base = "rv64i";
75 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
78 mmu-type = "riscv,sv39";
79 clock-frequency = <100000000>;
80 i-cache-size = <0x8000>;
81 i-cache-sets = <256>;
82 i-cache-line-size = <64>;
83 d-cache-size = <0x8000>;
84 d-cache-sets = <128>;
85 d-cache-line-size = <64>;
86 next-level-cache = <&l2_cache>;
88 cpu2_intc: interrupt-controller {
89 compatible = "andestech,cpu-intc",
90 "riscv,cpu-intc";
91 #interrupt-cells = <1>;
92 interrupt-controller;
100 riscv,isa-base = "rv64i";
101 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
104 mmu-type = "riscv,sv39";
105 clock-frequency = <100000000>;
106 i-cache-size = <0x8000>;
107 i-cache-sets = <256>;
108 i-cache-line-size = <64>;
109 d-cache-size = <0x8000>;
110 d-cache-sets = <128>;
111 d-cache-line-size = <64>;
112 next-level-cache = <&l2_cache>;
114 cpu3_intc: interrupt-controller {
115 compatible = "andestech,cpu-intc",
116 "riscv,cpu-intc";
117 #interrupt-cells = <1>;
118 interrupt-controller;
124 compatible = "simple-bus";
126 interrupt-parent = <&plic>;
127 #address-cells = <2>;
128 #size-cells = <2>;
130 plmt: timer@100000 { label
131 compatible = "andestech,qilai-plmt", "andestech,plmt0";
133 interrupts-extended = <&cpu0_intc 7>,
139 l2_cache: cache-controller@200000 {
140 compatible = "andestech,qilai-ax45mp-cache",
141 "andestech,ax45mp-cache", "cache";
144 cache-line-size = <64>;
145 cache-level = <2>;
146 cache-sets = <2048>;
147 cache-size = <0x200000>;
148 cache-unified;
151 plic_sw: interrupt-controller@400000 {
152 compatible = "andestech,qilai-plicsw",
155 interrupts-extended = <&cpu0_intc 3>,
161 plic: interrupt-controller@2000000 {
162 compatible = "andestech,qilai-plic",
165 #address-cells = <0>;
166 #interrupt-cells = <2>;
167 interrupt-controller;
168 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
179 clock-frequency = <50000000>;
180 reg-offset = <32>;
181 reg-shift = <2>;
182 reg-io-width = <4>;
183 no-loopback-test;