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/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,qe-ucc-qmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE QUICC Multichannel Controller (QMC)
10 - Herve Codina <herve.codina@bootlin.com>
14 serial controller using the same TDM physical interface routed from TSA.
19 - enum:
20 - fsl,mpc8321-ucc-qmc
21 - const: fsl,qe-ucc-qmc
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H A Dfsl,qe-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
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/linux/drivers/soc/fsl/qe/
H A Dtsa.c1 // SPDX-License-Identifier: GPL-2.0
3 * TSA driver
10 #include "tsa.h"
11 #include <dt-bindings/soc/cpm1-fsl,tsa.h>
12 #include <dt-bindings/soc/qe-fsl,tsa.h>
21 #include <soc/fsl/qe/ucc.h>
23 /* TSA SI RAM routing tables entry (CPM1) */
36 /* TSA SI RAM routing tables entry (QE) */
51 * - CPM1: 32bit register split in 2*16bit (16bit TDM)
52 * - QE: 4x16bit registers, one per TDM
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # QE Communication options
7 bool "QUICC Engine (QE) framework support"
13 The QUICC Engine (QE) is a new generation of communications
16 for a machine with a QE coprocessor.
37 tristate "CPM/QE TSA support"
42 Freescale CPM/QE Time Slot Assigner (TSA)
49 tristate "CPM/QE QMC support"
54 Freescale CPM/QE QUICC Multichannel Controller
69 QE USB Controller support
H A Ducc_slow.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * QE UCC Slow API Set - UCC Slow specific routines implementations.
20 #include <soc/fsl/qe/immap_qe.h>
21 #include <soc/fsl/qe/qe.h>
23 #include <soc/fsl/qe/ucc.h>
24 #include <soc/fsl/qe/ucc_slow.h>
44 struct ucc_slow_info *us_info = uccs->us_info; in ucc_slow_graceful_stop_tx()
47 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num); in ucc_slow_graceful_stop_tx()
55 struct ucc_slow_info *us_info = uccs->us_info; in ucc_slow_stop_tx()
58 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num); in ucc_slow_stop_tx()
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H A Dqmc.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <soc/fsl/qe/qmc.h>
12 #include <linux/dma-mapping.h>
23 #include <soc/fsl/qe/ucc_slow.h>
24 #include <soc/fsl/qe/qe.h>
26 #include "tsa.h"
28 /* SCC general mode register low (32 bits) (GUMR_L in QE) */
36 /* SCC general mode register high (32 bits) (identical to GUMR_H in QE) */
45 /* SCC event register (16 bits) (identical to UCCE in QE) */
55 /* UCC Extended Mode Register (8 bits, QE only) */
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H A Ducc_fast.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * QE UCC Fast API Set - UCC Fast specific routines implementations.
20 #include <soc/fsl/qe/immap_qe.h>
21 #include <soc/fsl/qe/qe.h>
23 #include <soc/fsl/qe/ucc.h>
24 #include <soc/fsl/qe/ucc_fast.h>
28 printk(KERN_INFO "UCC%u Fast registers:\n", uccf->uf_info->ucc_num); in ucc_fast_dump_regs()
29 printk(KERN_INFO "Base address: 0x%p\n", uccf->uf_regs); in ucc_fast_dump_regs()
32 &uccf->uf_regs->gumr, ioread32be(&uccf->uf_regs->gumr)); in ucc_fast_dump_regs()
34 &uccf->uf_regs->upsmr, ioread32be(&uccf->uf_regs->upsmr)); in ucc_fast_dump_regs()
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the linux ppc-specific parts of QE
5 obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_ic.o qe_io.o
6 obj-$(CONFIG_CPM) += qe_common.o
7 obj-$(CONFIG_CPM_TSA) += tsa.o
8 obj-$(CONFIG_CPM_QMC) += qmc.o
9 obj-$(CONFIG_UCC) += ucc.o
10 obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
11 obj-$(CONFIG_UCC_FAST) += ucc_fast.o
12 obj-$(CONFIG_QE_TDM) += qe_tdm.o
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/linux/drivers/net/wan/
H A Dfsl_ucc_hdlc.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 #include <soc/fsl/qe/immap_qe.h>
14 #include <soc/fsl/qe/qe.h>
16 #include <soc/fsl/qe/ucc.h>
17 #include <soc/fsl/qe/ucc_fast.h>
74 u16 tsa; member
129 #define TX_RING_MOD_MASK(size) (size - 1)
130 #define RX_RING_MOD_MASK(size) (size - 1)
H A Dfsl_ucc_hdlc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/dma-mapping.h>
26 #include <soc/fsl/qe/qe_tdm.h>
31 #define DRV_DESC "Freescale QE UCC HDLC Driver"
41 .tsa = 0,
93 ut_info = priv->ut_info; in uhdlc_init()
94 uf_info = &ut_info->uf_info; in uhdlc_init()
96 if (priv->tsa) { in uhdlc_init()
97 uf_info->tsa = 1; in uhdlc_init()
98 uf_info->ctsp = 1; in uhdlc_init()
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/linux/include/soc/fsl/qe/
H A Ducc_fast.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 #include <soc/fsl/qe/immap_qe.h>
16 #include <soc/fsl/qe/qe.h>
18 #include <soc/fsl/qe/ucc.h>
66 /* ucc_fast_channel_protocol_mode - UCC FAST mode */
86 /* ucc_fast_transparent_txrx - UCC Fast Transparent TX & RX */
151 int tsa; member
211 * uf_info - (In) pointer to the fast UCC info structure.
212 * uccf_ret - (Out) pointer to the fast UCC structure.
219 * uccf - (In) pointer to the fast UCC structure.
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H A Ducc_slow.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 #include <soc/fsl/qe/immap_qe.h>
17 #include <soc/fsl/qe/qe.h>
19 #include <soc/fsl/qe/ucc.h>
28 #define T_A 0x04000000 /* Address - the data transmitted as address
33 #define T_P 0x01000000 /* Preamble - send Preamble sequence before
89 /* 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1) */
93 /* 32-bit CCITT CRC (Ethernet and HDLC) */
161 int tsa; member
219 * us_info - (In) pointer to the slow UCC info structure.
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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