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/linux/drivers/clocksource/
H A Dsamsung_pwm_timer.c79 static struct samsung_pwm_clocksource pwm; variable
92 reg = readl(pwm.base + REG_TCFG0); in samsung_timer_set_prescale()
95 writel(reg, pwm.base + REG_TCFG0); in samsung_timer_set_prescale()
107 bits = (fls(divisor) - 1) - pwm.variant.div_base; in samsung_timer_set_divisor()
111 reg = readl(pwm.base + REG_TCFG1); in samsung_timer_set_divisor()
114 writel(reg, pwm.base + REG_TCFG1); in samsung_timer_set_divisor()
129 tcon = readl_relaxed(pwm.base + REG_TCON); in samsung_time_stop()
131 writel_relaxed(tcon, pwm.base + REG_TCON); in samsung_time_stop()
147 tcon = readl_relaxed(pwm.base + REG_TCON); in samsung_time_setup()
152 writel_relaxed(tcnt, pwm.base + REG_TCNTB(channel)); in samsung_time_setup()
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/linux/Documentation/devicetree/bindings/pwm/
H A Dpwm-amlogic.yaml4 $id: http://devicetree.org/schemas/pwm/pwm-amlogic.yaml#
7 title: Amlogic PWM
16 - amlogic,meson8b-pwm
17 - amlogic,meson-gxbb-pwm
18 - amlogic,meson-gxbb-ao-pwm
19 - amlogic,meson-axg-ee-pwm
20 - amlogic,meson-axg-ao-pwm
21 - amlogic,meson-g12a-ee-pwm
22 - amlogic,meson-g12a-ao-pwm-ab
23 - amlogic,meson-g12a-ao-pwm-cd
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H A Dpwm.txt1 Specifying PWM information for devices
4 1) PWM user nodes
7 PWM users should specify a list of PWM devices that they want to use
8 with a property containing a 'pwm-list':
10 pwm-list ::= <single-pwm> [pwm-list]
11 single-pwm ::= <pwm-phandle> <pwm-specifier>
12 pwm-phandle : phandle to PWM controller node
13 pwm-specifier : array of #pwm-cells specifying the given PWM
16 PWM properties should be named "pwms". The exact meaning of each pwms
18 An optional property "pwm-names" may contain a list of strings to label
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H A Drenesas,pwm-rcar.yaml4 $id: http://devicetree.org/schemas/pwm/renesas,pwm-rcar.yaml#
7 title: Renesas R-Car PWM Timer Controller
16 - renesas,pwm-r8a7742 # RZ/G1H
17 - renesas,pwm-r8a7743 # RZ/G1M
18 - renesas,pwm-r8a7744 # RZ/G1N
19 - renesas,pwm-r8a7745 # RZ/G1E
20 - renesas,pwm-r8a77470 # RZ/G1C
21 - renesas,pwm-r8a774a1 # RZ/G2M
22 - renesas,pwm-r8a774b1 # RZ/G2N
23 - renesas,pwm-r8a774c0 # RZ/G2E
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H A Dimx-pwm.yaml4 $id: http://devicetree.org/schemas/pwm/imx-pwm.yaml#
7 title: Freescale i.MX PWM controller
13 - $ref: pwm.yaml#
16 "#pwm-cells":
19 PWM_POLARITY_INVERTED. fsl,imx1-pwm does not support this flags.
25 - fsl,imx1-pwm
26 - fsl,imx27-pwm
29 - fsl,imx25-pwm
30 - fsl,imx31-pwm
31 - fsl,imx50-pwm
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H A Dallwinner,sun4i-a10-pwm.yaml4 $id: http://devicetree.org/schemas/pwm/allwinner,sun4i-a10-pwm.yaml#
7 title: Allwinner A10 PWM
14 "#pwm-cells":
19 - const: allwinner,sun4i-a10-pwm
20 - const: allwinner,sun5i-a10s-pwm
21 - const: allwinner,sun5i-a13-pwm
22 - const: allwinner,sun7i-a20-pwm
23 - const: allwinner,sun8i-h3-pwm
25 - const: allwinner,sun8i-a83t-pwm
26 - const: allwinner,sun8i-h3-pwm
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H A Dmediatek,mt2712-pwm.yaml4 $id: http://devicetree.org/schemas/pwm/mediatek,mt2712-pwm.yaml#
7 title: MediaTek PWM Controller
13 - $ref: pwm.yaml#
19 - mediatek,mt2712-pwm
20 - mediatek,mt6795-pwm
21 - mediatek,mt6991-pwm
22 - mediatek,mt7622-pwm
23 - mediatek,mt7623-pwm
24 - mediatek,mt7628-pwm
25 - mediatek,mt7629-pwm
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H A Dnvidia,tegra20-pwm.yaml4 $id: http://devicetree.org/schemas/pwm/nvidia,tegra20-pwm.yaml#
17 - nvidia,tegra20-pwm
18 - nvidia,tegra186-pwm
22 - nvidia,tegra30-pwm
23 - nvidia,tegra114-pwm
24 - nvidia,tegra124-pwm
25 - nvidia,tegra132-pwm
26 - nvidia,tegra210-pwm
28 - nvidia,tegra20-pwm
31 - const: nvidia,tegra194-pwm
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H A Dpwm-sifive.yaml5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
8 title: SiFive PWM controller
14 Unlike most other PWM controllers, the SiFive PWM controller currently
15 only supports one period for all channels in the PWM. All PWMs need to
18 achievable period. PWM RTL that corresponds to the IP block version
21 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
24 - $ref: pwm.yaml#
30 - sifive,fu540-c000-pwm
31 - sifive,fu740-c000-pwm
34 Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
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H A Dmediatek,pwm-disp.yaml4 $id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml#
13 - $ref: pwm.yaml#
19 - mediatek,mt2701-disp-pwm
20 - mediatek,mt6595-disp-pwm
21 - mediatek,mt8173-disp-pwm
22 - mediatek,mt8183-disp-pwm
25 - mediatek,mt6795-disp-pwm
26 - mediatek,mt8167-disp-pwm
27 - const: mediatek,mt8173-disp-pwm
30 - mediatek,mt6893-disp-pwm
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H A Dmarvell,pxa-pwm.yaml4 $id: http://devicetree.org/schemas/pwm/marvell,pxa-pwm.yaml#
7 title: Marvell PXA PWM
13 - $ref: pwm.yaml#
18 const: spacemit,k1-pwm
21 "#pwm-cells":
25 "#pwm-cells":
34 - marvell,pxa250-pwm
35 - marvell,pxa270-pwm
36 - marvell,pxa168-pwm
37 - marvell,pxa910-pwm
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H A Datmel,at91sam-pwm.yaml5 $id: http://devicetree.org/schemas/pwm/atmel,at91sam-pwm.yaml#
8 title: Atmel/Microchip PWM controller
14 - $ref: pwm.yaml#
21 - atmel,at91sam9rl-pwm
22 - atmel,sama5d3-pwm
23 - atmel,sama5d2-pwm
24 - microchip,sam9x60-pwm
27 - microchip,sama7d65-pwm
28 - microchip,sama7g5-pwm
29 - const: atmel,sama5d2-pwm
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/linux/Documentation/driver-api/
H A Dpwm.rst2 Pulse Width Modulation (PWM) interface
5 This provides an overview about the Linux PWM interface
9 the Linux PWM API (although they could). However, PWMs are often
12 this kind of flexibility the generic PWM API exists.
17 Users of the legacy PWM API use unique IDs to refer to PWM devices.
19 Instead of referring to a PWM device via its unique ID, board setup code
20 should instead register a static mapping that can be used to match PWM
24 PWM_LOOKUP("tegra-pwm", 0, "pwm-backlight", NULL,
39 consumer name. pwm_put() is used to free the PWM device. Managed variants of
42 After being requested, a PWM has to be configured using::
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/linux/drivers/pwm/
H A Dpwm-twl.c12 #include <linux/pwm.h>
32 #define TWL4030_PWM_TOGGLE(pwm, x) ((x) << (pwm)) argument
46 #define TWL6030_PWM_TOGGLE(pwm, x) ((x) << (pwm * 3)) argument
59 static int twl_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, in twl_pwm_config() argument
75 * When on cycle == off cycle the PWM will be always on in twl_pwm_config()
82 base = pwm->hwpwm * 3; in twl_pwm_config()
88 dev_err(pwmchip_parent(chip), "%s: Failed to configure PWM\n", pwm->label); in twl_pwm_config()
93 static int twl4030_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) in twl4030_pwm_enable() argument
102 dev_err(pwmchip_parent(chip), "%s: Failed to read GPBR1\n", pwm->label); in twl4030_pwm_enable()
106 val |= TWL4030_PWM_TOGGLE(pwm->hwpwm, TWL4030_PWMXCLK_ENABLE); in twl4030_pwm_enable()
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H A Dpwm-vt8500.c3 * drivers/pwm/pwm-vt8500.c
16 #include <linux/pwm.h>
28 #define REG_CTRL(pwm) (((pwm) << 4) + 0x00) argument
29 #define REG_SCALAR(pwm) (((pwm) << 4) + 0x04) argument
30 #define REG_PERIOD(pwm) (((pwm) << 4) + 0x08) argument
31 #define REG_DUTY(pwm) (((pwm) << 4) + 0x0C) argument
72 static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, in vt8500_pwm_config() argument
108 writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm)); in vt8500_pwm_config()
109 vt8500_pwm_busy_wait(chip, pwm->hwpwm, STATUS_SCALAR_UPDATE); in vt8500_pwm_config()
111 writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm)); in vt8500_pwm_config()
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H A Dpwm-twl-led.c8 * This driver is a complete rewrite of the former pwm-twl6030.c authorded by:
31 #include <linux/pwm.h>
36 * This driver handles the PWM driven LED terminals of TWL4030 and TWL6030.
69 static int twl4030_pwmled_config(struct pwm_chip *chip, struct pwm_device *pwm, in twl4030_pwmled_config() argument
85 * When on cycle == off cycle the PWM will be always on in twl4030_pwmled_config()
92 base = pwm->hwpwm * 2 + TWL4030_PWMA_REG; in twl4030_pwmled_config()
98 dev_err(pwmchip_parent(chip), "%s: Failed to configure PWM\n", pwm->label); in twl4030_pwmled_config()
103 static int twl4030_pwmled_enable(struct pwm_chip *chip, struct pwm_device *pwm) in twl4030_pwmled_enable() argument
110 dev_err(pwmchip_parent(chip), "%s: Failed to read LEDEN\n", pwm->label); in twl4030_pwmled_enable()
114 val |= TWL4030_LED_TOGGLE(pwm->hwpwm, TWL4030_LED_PINS); in twl4030_pwmled_enable()
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H A Dpwm-samsung.c9 * PWM driver for Samsung SoCs
21 #include <linux/pwm.h>
59 * struct samsung_pwm_channel - private data of PWM channel
71 * struct samsung_pwm_chip - private data of PWM chip
75 * @base: base address of mapped PWM registers
95 * PWM block is shared between pwm-samsung and samsung_pwm_timer drivers
101 * because all the supported SoCs contain only one instance of the PWM
121 struct pwm_device *pwm) in __pwm_samsung_manual_update() argument
123 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); in __pwm_samsung_manual_update()
200 "tclk of PWM %d is inoperational, using tdiv\n", chan); in pwm_samsung_calc_tin()
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H A Dpwm-jz4740.c4 * JZ4740 platform PWM support
20 #include <linux/pwm.h>
39 /* Enable all TCU channels for PWM use by default except channels 0/1 */ in jz4740_pwm_can_use_chn()
43 "ingenic,pwm-channels-mask", in jz4740_pwm_can_use_chn()
49 static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) in jz4740_pwm_request() argument
56 if (!jz4740_pwm_can_use_chn(chip, pwm->hwpwm)) in jz4740_pwm_request()
59 snprintf(name, sizeof(name), "timer%u", pwm->hwpwm); in jz4740_pwm_request()
74 jz->clk[pwm->hwpwm] = clk; in jz4740_pwm_request()
79 static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) in jz4740_pwm_free() argument
82 struct clk *clk = jz->clk[pwm->hwpwm]; in jz4740_pwm_free()
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H A Dpwm-omap-dmtimer.c9 * Also based on pwm-samsung.c
13 * PWM driver / controller, using the OMAP's dual-mode timers
15 * reloaded with the load value and the pwm output goes up.
20 * - When PWM is stopped, timer counter gets stopped immediately. This
21 * doesn't allow the current PWM period to complete and stops abruptly.
22 * - When PWM is running and changing both duty cycle and period,
25 * is updated while the pwm pin is high, current pwm period/duty_cycle
29 * - PWM OMAP DM timer cannot change the polarity when pwm is active. When
31 * - PWM is stopped abruptly(without completing the current cycle)
46 #include <linux/pwm.h>
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H A Dpwm-atmel.c8 * Links to reference manuals for the supported PWM chips can be found in
29 #include <linux/pwm.h>
32 /* The following is global registers for PWM controller */
40 /* The following register is PWM channel related registers */
50 /* The following registers for PWM v1 */
55 /* The following registers for PWM v2 */
87 * pending we delay disabling the PWM until the new configuration is
227 static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm, in atmel_pwm_update_cdty() argument
235 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_update_cdty()
237 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); in atmel_pwm_update_cdty()
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H A Dpwm-hibvt.c3 * PWM Controller Driver for HiSilicon BVT SoCs
15 #include <linux/pwm.h>
82 static void hibvt_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) in hibvt_pwm_enable() argument
86 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_enable()
90 static void hibvt_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) in hibvt_pwm_disable() argument
94 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_disable()
98 static void hibvt_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, in hibvt_pwm_config() argument
109 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm), in hibvt_pwm_config()
112 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm), in hibvt_pwm_config()
117 struct pwm_device *pwm, in hibvt_pwm_set_polarity() argument
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/linux/Documentation/ABI/testing/
H A Dsysfs-class-pwm1 What: /sys/class/pwm/
6 The pwm/ class sub-directory belongs to the Generic PWM
7 Framework and provides a sysfs interface for using PWM
10 What: /sys/class/pwm/pwmchip<N>/
15 A /sys/class/pwm/pwmchipN directory is created for each
16 probed PWM controller/chip where N is the base of the
17 PWM chip.
19 What: /sys/class/pwm/pwmchip<N>/npwm
24 The number of PWM channels supported by the PWM chip.
26 What: /sys/class/pwm/pwmchip<N>/export
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/linux/arch/loongarch/boot/dts/
H A Dloongson-2k0500.dtsi172 pwm@1ff5c000 {
173 compatible = "loongson,ls2k0500-pwm", "loongson,ls7a-pwm";
178 #pwm-cells = <3>;
182 pwm@1ff5c010 {
183 compatible = "loongson,ls2k0500-pwm", "loongson,ls7a-pwm";
188 #pwm-cells = <3>;
192 pwm@1ff5c020 {
193 compatible = "loongson,ls2k0500-pwm", "loongson,ls7a-pwm";
198 #pwm-cells = <3>;
202 pwm@1ff5c030 {
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/linux/Documentation/hwmon/
H A Dadt7470.rst25 There are four (4) PWM outputs that can be used to control fan speed.
27 A sophisticated control system for the PWM outputs is designed into the ADT7470
29 temperature sensors. Each PWM output is individually adjustable and
30 programmable. Once configured, the ADT7470 will adjust the PWM outputs in
32 feature can also be disabled for manual control of the PWM's.
40 automatic fan pwm control to set the fan speed. The driver will not read the
51 determining an optimal configuration for the automatic PWM control.
58 * PWM Control
60 * pwm#_auto_point1_pwm and pwm#_auto_point1_temp and
61 * pwm#_auto_point2_pwm and pwm#_auto_point2_temp -
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H A Ddme1737.rst47 and PWM output control functions. Using this parameter
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
69 For the DME1737, A8000 and SCH5027, fan[1-2] and pwm[1-2] are always present.
70 Fan[3-6] and pwm[3,5-6] are optional features and their availability depends on
74 For the SCH311x and SCH5127, fan[1-3] and pwm[1-3] are always present and
75 fan[4-6] and pwm[5-6] don't exist.
170 PWM Output Control
173 This chip features 5 PWM outputs. PWM outputs 1-3 are associated with fan
174 inputs 1-3 and PWM outputs 5-6 are associated with fan inputs 5-6. PWM outputs
176 the appropriate enable attribute accordingly. PWM outputs 5-6 can only operate
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