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/linux/Documentation/devicetree/bindings/regulator/
H A Drichtek,rtmv20-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
27 wakeup-source: true
32 enable-gpios:
36 richtek,ld-pulse-delay-us:
38 load current pulse delay in microsecond after strobe pin pulse high.
43 richtek,ld-pulse-width-us:
[all …]
/linux/Documentation/devicetree/bindings/i2c/
H A Dst,sti-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/st,sti-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrice Chotard <patrice.chotard@foss.st.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - st,comms-ssc-i2c
19 - st,comms-ssc4-i2c
30 clock-names:
33 clock-frequency:
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/linux/drivers/net/wireless/ath/
H A Ddfs_pattern_detector.h25 * TODO: this might need to be HW-dependent
30 * struct ath_dfs_pool_stats - DFS Statistics for global pools
43 * struct pulse_event - describing pulses reported by PHY
44 * @ts: pulse time stamp in us
46 * @width: pulse duration in us
48 * @chirp: chirp detected in pulse
53 u8 width; member
59 * struct radar_detector_specs - detector specs for a radar pattern type
61 * @width_min: minimum radar pulse width in [us]
62 * @width_max: maximum radar pulse width in [us]
[all …]
H A Ddfs_pri_detector.c27 #define DFS_POOL_STAT_DEC(c) (global_dfs_pool_stats.c--)
29 (MIN + PRI_TOLERANCE == MAX - PRI_TOLERANCE ? \
33 * struct pulse_elem - elements in pulse queue
41 * pde_get_multiple() - get number of multiples considering a given tolerance
42 * Return value: factor if abs(val - factor*fraction) <= tolerance, 0 otherwise
53 delta = (val < fraction) ? (fraction - val) : (val - fraction); in pde_get_multiple()
63 if ((fraction - remainder) <= tolerance) in pde_get_multiple()
73 * DOC: Singleton Pulse and Sequence Pools
97 singleton_pool_references--; in pool_deregister_ref()
105 list_del(&p->head); in pool_deregister_ref()
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/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76x02_dfs.c1 // SPDX-License-Identifier: ISC
154 struct mt76x02_dfs_pattern_detector *dfs_pd = &dev->dfs_pd; in mt76x02_dfs_seq_pool_put()
156 list_add(&seq->head, &dfs_pd->seq_pool); in mt76x02_dfs_seq_pool_put()
158 dfs_pd->seq_stats.seq_pool_len++; in mt76x02_dfs_seq_pool_put()
159 dfs_pd->seq_stats.seq_len--; in mt76x02_dfs_seq_pool_put()
165 struct mt76x02_dfs_pattern_detector *dfs_pd = &dev->dfs_pd; in mt76x02_dfs_seq_pool_get()
168 if (list_empty(&dfs_pd->seq_pool)) { in mt76x02_dfs_seq_pool_get()
169 seq = devm_kzalloc(dev->mt76.dev, sizeof(*seq), GFP_ATOMIC); in mt76x02_dfs_seq_pool_get()
171 seq = list_first_entry(&dfs_pd->seq_pool, in mt76x02_dfs_seq_pool_get()
174 list_del(&seq->head); in mt76x02_dfs_seq_pool_get()
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/linux/drivers/media/usb/au0828/
H A Dau0828-input.c1 // SPDX-License-Identifier: GPL-2.0+
7 // Based on em28xx-input.c.
17 #include <media/rc-core.h>
47 struct i2c_msg msg = { .addr = ir->i2c_dev_addr, .flags = 0, in au8522_rc_write()
50 rc = i2c_transfer(ir->dev->i2c_client.adapter, &msg, 1); in au8522_rc_write()
55 return (rc == 1) ? 0 : -EIO; in au8522_rc_write()
63 struct i2c_msg msg[2] = { { .addr = ir->i2c_dev_addr, .flags = 0, in au8522_rc_read()
65 { .addr = ir->i2c_dev_addr, .flags = I2C_M_RD, in au8522_rc_read()
75 rc = i2c_transfer(ir->dev->i2c_client.adapter, msg, 2); in au8522_rc_read()
80 return (rc == 2) ? 0 : -EIO; in au8522_rc_read()
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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Datmel,ebi.txt5 The EBI provides a glue-less interface to asynchronous memories through the SMC
10 - compatible: "atmel,at91sam9260-ebi"
11 "atmel,at91sam9261-ebi"
12 "atmel,at91sam9263-ebi0"
13 "atmel,at91sam9263-ebi1"
14 "atmel,at91sam9rl-ebi"
15 "atmel,at91sam9g45-ebi"
16 "atmel,at91sam9x5-ebi"
17 "atmel,sama5d3-ebi"
18 "microchip,sam9x60-ebi"
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/linux/arch/arm/boot/dts/st/
H A Dstihxxx-b2120.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/clock/stih407-clks.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/media/c8sectpfe.h>
11 compatible = "gpio-leds";
12 led-red {
15 linux,default-trigger = "heartbeat";
17 led-green {
19 default-state = "off";
24 compatible = "simple-audio-card";
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H A Dstih418-b2199.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "st,stih418-b2199", "st,stih418";
14 stdout-path = &sbc_serial0;
28 compatible = "gpio-leds";
29 led-red {
32 linux,default-trigger = "heartbeat";
34 led-green {
36 default-state = "off";
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/linux/drivers/media/i2c/cx25840/
H A Dcx25840-ir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <media/drv-intf/cx25840.h>
14 #include <media/rc-core.h>
16 #include "cx25840-core.h"
117 return state ? state->ir_state : NULL; in to_ir_state()
135 d--; in count_to_clock_divider()
193 * FIFO register pulse width count computations
199 * the pulse width counter as read from the FIFO. The two lsb's are in clock_divider_to_resolution()
212 * The 2 lsb's of the pulse width timer count are not readable, hence in pulse_width_count_to_ns()
231 * The 2 lsb's of the pulse width timer count are not accessible, hence
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Ddfs.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
19 #include "hw-ops.h"
36 * - 20MHz chirp width over a pulse width of 50us
37 * - 5MHz chirp width over a pulse width of 100us
49 /* width range to be checked for chirping */
83 is_ctl = fft_bitmap_weight(fft->lower_bins) != 0; in ath9k_get_max_index_ht40()
84 is_ext = fft_bitmap_weight(fft->upper_bins) != 0; in ath9k_get_max_index_ht40()
88 int mag_lower = fft_max_magnitude(fft->lower_bins); in ath9k_get_max_index_ht40()
89 int mag_upper = fft_max_magnitude(fft->upper_bins); in ath9k_get_max_index_ht40()
97 return fft_max_index(fft->lower_bins); in ath9k_get_max_index_ht40()
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/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr3-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr3-timings
19 Maximum DDR clock frequency for the speed-bin, in Hz.
20 Property is deprecated, use max-freq.
23 max-freq:
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H A Djedec,lpddr2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - elpida,ECB240ABACN
[all …]
H A Djedec,lpddr3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - samsung,K3QF2F20DB
[all …]
/linux/drivers/media/pci/cx23885/
H A Dcx23888-ir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include "cx23888-ir.h"
16 #include <media/v4l2-device.h>
17 #include <media/rc-core.h>
174 d--; in count_to_clock_divider()
232 * FIFO register pulse width count computations
238 * the pulse width counter as read from the FIFO. The two lsb's are in clock_divider_to_resolution()
251 * The 2 lsb's of the pulse width timer count are not readable, hence in pulse_width_count_to_ns()
267 * The 2 lsb's of the pulse width timer count are not readable, hence in pulse_width_count_to_us()
278 * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
[all …]
/linux/drivers/media/rc/
H A Drc-core-priv.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 /* Define the max number of pulse/space transitions to buffer */
17 #include <media/rc-core.h>
20 * rc_open - Opens a RC device
27 * rc_close - Closes a RC device
51 /* fifo for the pulse/space durations */
169 return d1 > (d2 - margin); in geq_margin()
174 return ((d1 > (d2 - margin)) && (d1 < (d2 + margin))); in eq_margin()
179 return x->pulse != y->pulse; in is_transition()
184 if (duration > ev->duration) in decrease_duration()
[all …]
H A Dite-cir.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #define ITE_DRIVER_NAME "ite-cir"
34 /* hw-specific operation function pointers; most of these must be
43 /* make rx enter the idle state; keep listening for a pulse, but stop
98 /* duty cycle, 0-100 */
114 /* low-speed carrier frequency limits (Hz) */
118 /* high-speed carrier frequency limits (Hz) */
130 * n in RDCR produces a tolerance of +/- n * 6.25% around the center
135 * frequency A = (H - L) / (H + L). We can use this in order to honor the
136 * s_rx_carrier_range() call in ir-core. We'll suppose that any request
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H A Dene_ir.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #define ENE_STATUS 0 /* hardware status - unused */
50 #define ENE_FW_SMPL_BUF_FAN_PLS 0x8000 /* combined sample is pulse */
98 #define ENE_CIRCFG2_FAST_SAMPL1 0x40 /* Fast leading pulse detection for RC6 */
101 /* Knobs for protocol decoding - will document when/if will use them */
108 /* Actual register which contains RLC RX data - read by firmware */
112 /* RLC configuration - sample period (1us resolution) + idle mode */
120 #define ENE_CIRRLC_OUT_PULSE 0x80 /* Transmitted sample is pulse */
125 * Low nibble - number of carrier pulses to average
126 * High nibble - number of initial carrier pulses to discard
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/linux/drivers/misc/eeprom/
H A Deeprom_93cx6.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2004 - 2006 rt2x00 SourceForge Project
24 eeprom->reg_data_clock = 1; in eeprom_93cx6_pulse_high()
25 eeprom->register_write(eeprom); in eeprom_93cx6_pulse_high()
28 * Add a short delay for the pulse to work. in eeprom_93cx6_pulse_high()
37 eeprom->reg_data_clock = 0; in eeprom_93cx6_pulse_low()
38 eeprom->register_write(eeprom); in eeprom_93cx6_pulse_low()
41 * Add a short delay for the pulse to work. in eeprom_93cx6_pulse_low()
53 eeprom->register_read(eeprom); in eeprom_93cx6_startup()
54 eeprom->reg_data_in = 0; in eeprom_93cx6_startup()
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dsama5d3xcm.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module
14 stdout-path = "serial0:115200n8";
23 clock-frequency = <32768>;
27 clock-frequency = <12000000>;
34 cs-gpios = <&pioD 13 0>, <0>, <0>, <0>;
39 compatible = "atmel,tcb-timer";
44 compatible = "atmel,tcb-timer";
51 pinctrl-0 = <&pinctrl_ebi_addr &pinctrl_ebi_cs0>;
52 pinctr-name = "default";
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/linux/include/video/
H A Ds1d13xxxfb.h4 * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
44 #define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/l…
45 #define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=N…
47 #define S1DREG_TFT_FPLINE_PWIDTH 0x0036 /* TFT FPLINE Pulse Width Register. */
50 #define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines …
52 #define S1DREG_TFT_FPFRAME_PWIDTH 0x003C /* TFT FPFRAME Pulse Width Register */
63 #define S1DREG_CRT_DISP_HWIDTH 0x0050 /* CRT/TV Horizontal Display Width Register: ((val)+1)*8)=pi…
64 #define S1DREG_CRT_NDISP_HPER 0x0052 /* CRT/TV Horizontal Non-Display Period Register */
66 #define S1DREG_CRT_HRTC_PWIDTH 0x0054 /* CRT/TV HRTC Pulse Width Register */
69 #define S1DREG_CRT_NDISP_VPER 0x0058 /* CRT/TV Vertical Non-Display Period Register */
[all …]
/linux/Documentation/devicetree/bindings/mtd/
H A Dlpc32xx-slc.txt4 - compatible: "nxp,lpc3220-slc"
5 - reg: Address and size of the controller
6 - nand-on-flash-bbt: Use bad block table on flash
7 - gpios: GPIO specification for NAND write protect
11 - nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY)
12 - nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY)
15 - nxp,wwidth: Write pulse width (W_WIDTH)
16 - nxp,whold: Write hold time (W_HOLD)
17 - nxp,wsetup: Write setup time (W_SETUP)
18 - nxp,rwidth: Read pulse width (R_WIDTH)
[all …]
/linux/Documentation/driver-api/
H A Dmiscellaneous.rst4 .. kernel-doc:: include/linux/parport.h
7 .. kernel-doc:: drivers/parport/ieee1284.c
10 .. kernel-doc:: drivers/parport/share.c
13 .. kernel-doc:: drivers/parport/daisy.c
19 .. kernel-doc:: drivers/tty/serial/8250/8250_core.c
24 Pulse-Width Modulation (PWM)
27 Pulse-width modulation is a modulation technique primarily used to
33 are expected to embed this structure in a driver-specific structure.
44 .. kernel-doc:: include/linux/pwm.h
47 .. kernel-doc:: drivers/pwm/core.c
/linux/drivers/pwm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "Pulse-Width Modulation (PWM) Support"
5 Generic Pulse-Width Modulation (PWM) support.
7 In Pulse-Width Modulation, a variation of the width of pulses
8 in a rectangular pulse signal is used as a means to alter the
48 will be called pwm-ab8500.
67 will be called pwm-apple.
77 will be called pwm-atmel.
85 (Atmel High-end LCD Controller). This PWM output is mainly used
89 will be called pwm-atmel-hlcdc.
[all …]
H A Dpwm-tegra.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/pwm/pwm-tegra.c
5 * Tegra pulse-width-modulation controller driver
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
10 * Overview of Tegra Pulse Width Modulator Register:
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
23 * PWM pulse width: 8 bits are usable [23:16] for varying pulse width.
[all …]

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