Lines Matching +full:pulse +full:- +full:width

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #define ITE_DRIVER_NAME "ite-cir"
34 	/* hw-specific operation function pointers; most of these must be
43 	/* make rx enter the idle state; keep listening for a pulse, but stop
98 	/* duty cycle, 0-100 */
114 /* low-speed carrier frequency limits (Hz) */
118 /* high-speed carrier frequency limits (Hz) */
130  * n in RDCR produces a tolerance of +/- n * 6.25% around the center
135  * frequency A = (H - L) / (H + L). We can use this in order to honor the
136  * s_rx_carrier_range() call in ir-core. We'll suppose that any request
147 /* values for pulse widths */
170  * Environment Control - Low Pin Count Input / Output
171  * (EC - LPC I/O)
202 #define IT87_HCFS	0x40	/* high-speed carrier frequency select */
206 #define IT87_TXMPM	0x03	/* transmitter modulation pulse mode mask */
207 #define IT87_TXMPM_DEFAULT 0x00	/* modulation pulse mode default */
212 					 * 0x00 -> 1, 0x10 -> 7, 0x20 -> 17,
213 					 * 0x30 -> 25 */
218 #define IT87_TXMPW	0x07	/* transmitter modulation pulse width mask */
219 #define IT87_TXMPW_DEFAULT 0x04	/* default modulation pulse width */
228 #define IT87_RXFTO	0x80	/* receiver FIFO time-out */
280 					 * 0x00 -> 1, 0x04 -> 7, 0x08 -> 17,
281 					 * 0x0c -> 25 */
309 #define IT85_TXMPW	0x07	/* transmitter modulation pulse width mask */
310 #define IT85_TXMPW_DEFAULT 0x04	/* default modulation pulse width */
311 #define IT85_TXMPM	0x18	/* transmitter modulation pulse mode mask */
312 #define IT85_TXMPM_DEFAULT 0x00	/* modulation pulse mode default */
329 #define IT85_RXFTO	0x80	/* receiver FIFO time-out */
349  * suggest that it maps the 16 registers of IT8512 onto two 8-register banks,
350  * selectable by a single bank-select bit that's mapped onto both banks. The
353  * reserved high-order bit are placed at the same offset in both banks in
408  * a specific firmware running on the IT8512's embedded micro-controller.
409  * In addition of the embedded micro-controller, the IT8512 chip contains a
412  * micro-controller. The CIR module is only accessible by the
413  * micro-controller.
415  * The battery-backed SRAM module is accessible by the host CPU and the
416  * micro-controller. So one of the MC's firmware role is to act as a bridge
420  * communication protocol is not, so it was reverse-engineered.