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Searched full:ptw (Results 1 – 22 of 22) sorted by relevance

/linux/arch/sh/include/cpu-sh4/cpu/
H A Dsh7724.h97 /* PTW */
134 /* ATAPI (PTA/PTB/PTK/PTR/PTS/PTW) */
249 /* SDHI1 (PTW) */
253 /* MMC (PTW/PTX)*/
H A Dsh7757.h94 /* PTW */
232 /* PTW (mobule: LBSC, EVC, SCIF) */
H A Dsh7722.h89 /* PTW */
H A Dsh7723.h95 /* PTW */
/linux/Documentation/devicetree/bindings/iommu/
H A Darm,smmu.yaml301 the smmu ptw
326 - description: bus clock required for the smmu ptw
343 the smmu ptw
370 - description: bus clock required for the smmu ptw
390 the smmu ptw
447 the smmu ptw
/linux/tools/perf/scripts/python/bin/
H A Dintel-pt-events-record8 echo "Options must include the Intel PT event e.g. -e intel_pt/pwr_evt,ptw/"
/linux/arch/csky/include/asm/
H A Dbarrier.h80 * Using three sync.is to prevent speculative PTW
/linux/drivers/usb/chipidea/
H A Dbits.h77 /* PTS and PTW for non lpm version only */
/linux/arch/loongarch/kernel/
H A Dproc.c70 if (cpu_has_ptw) seq_printf(m, " ptw"); in show_cpuinfo()
/linux/arch/sh/boards/
H A Dboard-sh7757lcr.c446 /* SCIF3/4 (PTJ, PTW) */ in sh7757lcr_devices_setup()
529 /* EVC (PTV, PTW) */ in sh7757lcr_devices_setup()
/linux/arch/arm64/include/asm/
H A Dkvm_arm.h76 #define HCR_PTW __HCR(PTW)
96 * PTW: Take a stage2 fault if a stage1 walk steps in device memory
/linux/drivers/pinctrl/renesas/
H A Dpfc-sh7757.c461 /* PTW (mobule: LBSC, EVC, SCIF) */
691 /* PTW GPIO */
1012 /* PTW FN */
1290 /* PTW */
1623 /* PTW (mobule: LBSC, EVC, SCIF) */
H A Dpfc-sh7724.c483 /*PTW*/
712 /* PTW GPIO */
1075 /* PTW FN */
1332 /* PTW */
H A Dpfc-sh7723.c520 /* PTW GPIO */
862 /* PTW FN */
1093 /* PTW */
H A Dpfc-sh7722.c428 /* PTW */
919 /* PTW */
/linux/arch/arm64/kvm/
H A Dat.c16 wr->ptw = s1ptw; in fail_s1_walk()
855 par |= wr->ptw ? SYS_PAR_EL1_PTW : 0; in compute_par_s1()
1416 * fault, we know for sure that the PTW was able to walk the S1 in __kvm_at_s1e01()
/linux/drivers/iommu/
H A Dexynos-iommu.c217 "PTW",
225 "PTW",
H A Dsun50i-iommu.c331 dev_warn(iommu->dev, "PTW cache invalidation timed out!\n"); in sun50i_iommu_zap_ptw_cache()
/linux/arch/arm/mm/
H A Dproc-v7.S85 ALT_SMP(W(nop)) @ MP extensions imply L1 PTW
/linux/arch/mips/mm/
H A Dtlbex.c2377 …pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PT… in print_htw_config()
2405 * setup GDW and PTW appropriately. UDW and MDW will remain 0. in config_htw_params()
/linux/arch/arm64/tools/
H A Dsysreg3815 Field 2 PTW
/linux/arch/arm64/kernel/
H A Dcpufeature.c1871 * PTW barfs on the nVHE EL2 S1 page table format. Pretend in has_nv1()