/linux/Documentation/devicetree/bindings/clock/ |
H A D | qcom,gcc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Stephen Boyd <sboyd@kernel.org> 11 - Taniya Das <quic_tdas@quicinc.com> 15 clocks, resets and power domains. 18 '#clock-cells': 21 '#reset-cells': 24 '#power-domain-cells': 30 protected-clocks: [all …]
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H A D | qcom,sar2130p-gcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/qcom,sar2130p-gcc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> 13 Qualcomm global clock control module provides the clocks, resets and 16 See also: include/dt-bindings/clock/qcom,sar2130p-gcc.h 20 const: qcom,sar2130p-gcc 22 clocks: 24 - description: XO reference clock [all …]
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/linux/drivers/clk/qcom/ |
H A D | common.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. 10 #include <linux/clk-provider.h> 11 #include <linux/interconnect-clk.h> 13 #include <linux/reset-controller.h> 17 #include "clk-alpha-pll.h" 18 #include "clk-branch.h" 19 #include "clk-rcg.h" 20 #include "clk-regmap.h" 37 if (!f->freq) in qcom_find_freq() [all …]
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/linux/sound/pci/echoaudio/ |
H A D | echoaudio.h | 3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004 21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, 22 MA 02111-1307, USA. 26 Translation from C++ and adaptation for use in ALSA-Driver 34 +-----------+ 35 record | |<-------------------- Inputs 36 <-------| | | 39 ------->| | +-------+ 40 play | |--->|monitor|-------> Outputs 41 +-----------+ | mixer | [all …]
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/linux/Documentation/driver-api/ |
H A D | clk.rst | 22 clk which unifies the framework-level accounting and infrastructure that 28 The second half of the interface is comprised of the hardware-specific 30 hardware-specific structures needed to model a particular clock. For 32 clk_ops, such as .enable or .set_rate, implies the hardware-specific 35 hardware-specific bits for the hypothetical "foo" hardware. 62 api itself defines several driver-facing functions which operate on 66 clk_ops pointer in struct clk_core to perform the hardware-specific parts of 67 the operations defined in clk-provider.h:: 107 which abstract the details of struct clk from the hardware-specific bits, and 109 drivers/clk/clk-gate.c:: [all …]
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/linux/arch/arm64/boot/dts/qcom/ |
H A D | qcs404-evb.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 6 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 19 stdout-path = "serial0"; 22 vph_pwr: vph-pwr-regulator { 23 compatible = "regulator-fixed"; 24 regulator-name = "vph_pwr"; 25 regulator-always-on; 26 regulator-boot-on; [all …]
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H A D | sdm845-lg-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 16 /delete-node/ &adsp_mem; 17 /delete-node/ &cdsp_mem; 18 /delete-node/ &gpu_mem; 19 /delete-node/ &ipa_fw_mem; 20 /delete-node/ &mba_region; 21 /delete-node/ &mpss_region; [all …]
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H A D | sdm850-samsung-w737.dts | 1 // SPDX-License-Identifier: BSD-3-Clause 8 /dts-v1/; 10 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 11 #include <dt-bindings/input/gpio-keys.h> 12 #include <dt-bindings/input/input.h> 13 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 14 #include <dt-bindings/sound/qcom,q6afe.h> 15 #include <dt-bindings/sound/qcom,q6asm.h> 17 #include "sdm845-wcd9340.dtsi" 24 /delete-node/ &qseecom_mem; [all …]
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/linux/drivers/clk/ |
H A D | clk.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com> 4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> 6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst 9 #include <linux/clk/clk-conf.h> 12 #include <linux/clk-provider.h> 123 if (!core->rpm_enabled) in clk_pm_runtime_get() 126 return pm_runtime_resume_and_get(core->dev); in clk_pm_runtime_get() 131 if (!core->rpm_enabled) in clk_pm_runtime_put() 134 pm_runtime_put_sync(core->dev); in clk_pm_runtime_put() [all …]
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H A D | clk-stm32h7.c | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <linux/clk-provider.h> 18 #include <dt-bindings/clock/stm32h7-clks.h> 139 /* Micro-controller output clock parent */ 178 bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy)); in ready_gate_clk_enable() 183 } while (bit_status && --timeout); in ready_gate_clk_enable() 201 bit_status = !!(readl(gate->reg) & BIT(rgate->bit_rdy)); in ready_gate_clk_disable() 206 } while (bit_status && --timeout); in ready_gate_clk_disable() 227 return ERR_PTR(-ENOMEM); in clk_register_ready_gate() 235 rgate->bit_rdy = bit_rdy; in clk_register_ready_gate() [all …]
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/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx6dl-b1x5pv2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT 6 // Copyright 2018-2021 General Electric Company 7 // Copyright 2018-2021 Collabora 9 #include <dt-bindings/input/input.h> 10 #include "imx6dl-qmx6.dtsi" 14 stdout-path = &uart3; 20 operating-points = < 25 fsl,soc-operating-points = < 26 /* ARM kHz SOC-PU uV */ 33 operating-points = < [all …]
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/linux/include/linux/ |
H A D | ti_wilink_st.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 6 * and also serves the sub-modules of the shared transport driver. 8 * Copyright (C) 2009-2010 Texas Instruments 18 * enum proto-type - The protocol on WiLink chips which share a 29 * struct st_proto_s - Per Protocol structure from BT/FM/GPS to ST 94 * struct st_data_s - ST core internal structure 104 * This needs to be protected, hence the lock inside wakeup func. 152 * wrapper around tty->ops->write_room to check 157 * st_int_write - 158 * point this to tty->driver->write or tty->ops->write [all …]
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/linux/kernel/time/ |
H A D | posix-cpu-timers.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Implement CPU time clocks for the POSIX clock interface. 8 #include <linux/posix-timers.h> 20 #include "posix-timers.h" 28 pct->bases[CPUCLOCK_PROF].nextevt = cpu_limit * NSEC_PER_SEC; in posix_cputimers_group_init() 29 pct->timers_active = true; in posix_cputimers_group_init() 35 * tsk->signal->posix_cputimers.bases[clock].nextevt expiration cache if 39 * Returns 0 on success, -ESRCH on failure. Can fail if the task is exiting and 48 return -ESRCH; in update_rlimit_cpu() 102 ret = pid_for_clock(clock, false) ? 0 : -EINVAL; in validate_clock_permissions() [all …]
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H A D | timekeeping.c | 1 // SPDX-License-Identifier: GPL-2.0 31 #include "tick-internal.h" 67 return ktime_get_aux_ts64(CLOCK_AUX + tkid - TIMEKEEPER_AUX_FIRST, ts); in tk_get_aux_ts64() 72 return tk->id >= TIMEKEEPER_AUX_FIRST && tk->id <= TIMEKEEPER_AUX_LAST; in tk_is_aux() 88 tk->offs_aux = offs; in tk_update_aux_offs() 89 tk->monotonic_to_aux = ktime_to_timespec64(offs); in tk_update_aux_offs() 96 * struct tk_fast - NMI safe timekeeper 109 /* Suspend-time cycles value for halted fast timekeeper. */ 174 * Multigrain timestamps require tracking the latest fine-grained timestamp 175 * that has been issued, and never returning a coarse-grained timestamp that is [all …]
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H A D | posix-timers.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * 2002-10-15 Posix Clocks & timers 7 * 2004-06-01 Fix CLOCK_REALTIME clock/timer TIMER_ABSTIME bug. 10 * These are all the functions necessary to implement POSIX clocks & timers 20 #include <linux/posix-clock.h> 21 #include <linux/posix-timers.h> 31 #include "posix-timers.h" 73 __cond_lock(&__timr->it_lock, __timr = __lock_timer(tid)); \ 80 spin_unlock_irq(&timr->it_lock); in unlock_timer() 84 scoped_cond_guard(lock_timer, return -EINVAL, _id) [all …]
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/linux/include/ufs/ |
H A D | ufshcd.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 16 #include <linux/blk-crypto-profile.h> 17 #include <linux/blk-m [all...] |
/linux/drivers/clk/bcm/ |
H A D | clk-kona.c | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #include "clk-kona.h" 12 #include <linux/clk-provider.h> 16 * "Policies" affect the frequencies of bus clocks provided by a 28 /* Produces a mask of set bits covering a range of a 32-bit value */ 31 return ((1 << width) - 1) << shift; in bitfield_mask() 53 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value() 61 return (u64)div->u.fixed; in scaled_div_min() 72 return (u64)div->u.fixed; in scaled_div_max() 74 reg_div = ((u32)1 << div->u.s.width) - 1; in scaled_div_max() [all …]
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/linux/drivers/nvmem/ |
H A D | imx-ocotp.c | 1 // SPDX-License-Identifier: GPL-2.0-only 14 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc 21 #include <linux/nvmem-provider.h> 74 #define DEF_STROBE_PROG 10000 /* IPG clocks */ 107 void __iomem *base = priv->base; in imx_ocotp_wait_for_busy() 109 bm_ctrl_busy = priv->params->ctrl.bm_busy; in imx_ocotp_wait_for_busy() 110 bm_ctrl_error = priv->params->ctrl.bm_error; in imx_ocotp_wait_for_busy() 114 for (count = 10000; count >= 0; count--) { in imx_ocotp_wait_for_busy() 124 * - A write is performed to a shadow register during a shadow in imx_ocotp_wait_for_busy() 128 * - A write is performed to a shadow register which has been in imx_ocotp_wait_for_busy() [all …]
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/linux/tools/arch/x86/kcpuid/ |
H A D | cpuid.csv | 1 # SPDX-License-Identifier: CC0-1.0 2 # Generator: x86-cpuid-db v2.4 5 # Auto-generated file. 6 # Please submit all updates and bugfixes to https://x86-cpuid.org 16 0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 - 3 17 0x0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor ID string bytes 8 - 11 18 0x0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 - [all...] |
/linux/drivers/firmware/xilinx/ |
H A D | zynqmp.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2014-2022 Xilinx, Inc. 6 * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. 14 #include <linux/arm-smccc.h> 28 #include <linux/firmware/xlnx-zynqmp.h> 29 #include <linux/firmware/xlnx-event-manager.h> 30 #include "zynqmp-debug.h" 37 /* BOOT_PIN_CTRL- Used to control the mode pins after boot */ 39 /* BOOT_PIN_CTRL_MASK- out_val[11:8], out_en[3:0] */ 54 * struct zynqmp_devinfo - Structure for Zynqmp device instance [all …]
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/linux/Documentation/admin-guide/ |
H A D | kernel-parameters.txt | 16 force -- enable ACPI if default was off 17 on -- enable ACPI but allow fallback to DT [arm64,riscv64] 18 off -- disable ACPI if default was on 19 noirq -- do not use ACPI for IRQ routing 20 strict -- Be less tolerant of platforms that are not 22 rsdt -- prefer RSDT over (default) XSDT 23 copy_dsdt -- copy DSDT to memory 24 nocmcff -- Disable firmware first mode for corrected 28 nospcr -- disable console in ACPI SPCR table as 45 If set to vendor, prefer vendor-specific driver [all …]
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/linux/sound/soc/sti/ |
H A D | uniperif_player.c | 1 // SPDX-License-Identifier: GPL-2.0-only 17 * Some hardware-related definitions 27 #define UNIPERIF_PLAYER_CLK_ADJ_MIN -999999 58 * In case of error audio stream is stopped; stop action is protected via PCM 68 spin_lock(&player->irq_lock); in uni_player_irq_handler() 69 if (!player->substream) in uni_player_irq_handler() 72 snd_pcm_stream_lock(player->substream); in uni_player_irq_handler() 73 if (player->state == UNIPERIF_STATE_STOPPED) in uni_player_irq_handler() 82 dev_err(player->dev, "FIFO underflow error detected\n"); in uni_player_irq_handler() 85 if (player->underflow_enabled) { in uni_player_irq_handler() [all …]
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/linux/arch/x86/kvm/ |
H A D | xen.c | 1 // SPDX-License-Identifier: GPL-2.0 40 struct gfn_to_pfn_cache *gpc = &kvm->arch.xen.shinfo_cache; in kvm_xen_shared_info_init() 46 int idx = srcu_read_lock(&kvm->srcu); in kvm_xen_shared_info_init() 48 read_lock_irq(&gpc->lock); in kvm_xen_shared_info_init() 50 read_unlock_irq(&gpc->lock); in kvm_xen_shared_info_init() 56 read_lock_irq(&gpc->lock); in kvm_xen_shared_info_init() 65 /* Paranoia checks on the 32-bit struct layout */ in kvm_xen_shared_info_init() 71 /* Paranoia checks on the 64-bit struct layout */ in kvm_xen_shared_info_init() 75 if (IS_ENABLED(CONFIG_64BIT) && kvm->arch.xen.long_mode) { in kvm_xen_shared_info_init() 76 struct shared_info *shinfo = gpc->khva; in kvm_xen_shared_info_init() [all …]
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/linux/drivers/net/ethernet/sun/ |
H A D | cassini.c | 1 // SPDX-License-Identifier: GPL-2.0+ 13 * load balancing (non-VLAN mode) 16 * page-based RX descriptor engine with separate completion rings 22 * -- driver allocates pages at a time and keeps reference counts 24 * -- the upper protocol layers assume that the header is in the skb 27 * -- driver appends the rest of the data pages as frags to skbuffs 29 * -- on page reclamation, the driver swaps the page with a spare page. 37 * TX has 4 queues. currently these queues are used in a round-robin 41 * alternatively, the queues can be configured via use of the all-purpose 49 * encrypted and non-encrypted packets, but we use them for buffering [all …]
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/linux/drivers/gpu/drm/renesas/rcar-du/ |
H A D | rcar_du_crtc.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * R-Car Display Unit CRTCs 5 * Copyright (C) 2013-2015 Renesas Electronics Corporation 35 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_read() 37 return rcar_du_read(rcdu, rcrtc->mmio_offset + reg); in rcar_du_crtc_read() 42 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_write() 44 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data); in rcar_du_crtc_write() 49 struct rcar_du_device *rcdu = rcrtc->dev; in rcar_du_crtc_clr() 51 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, in rcar_du_crtc_clr() 52 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr); in rcar_du_crtc_clr() [all …]
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