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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_udma_regs_s2m.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
85 * [0x0] DMA state
86 * 00 - No pending tasks
92 /* [0x4] CPU request to change DMA state */
96 * [0xc] S2M DMA error log mask.
98 * This register determines if these errors cause the S2M DMA to log the
100 * 0 - Log is enable
101 * 1 - Log is masked.
106 * [0x14] DMA header log
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H A Dal_hal_udma_regs_m2s.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
83 * [0x0] DMA state.
84 * 00 - No pending tasks
90 /* [0x4] CPU request to change DMA state */
94 * [0xc] M2S DMA error log mask.
96 * This register determines if these errors cause the M2S DMA to log the
98 * 0 - Log is enabled.
99 * 1 - Log is masked.
104 * [0x14] DMA header log.
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H A Dal_hal_udma_config.h9 found at http://www.gnu.org/licenses/gpl-2.0.html
43 * @brief C Header file for the Universal DMA HAL driver for configuration APIs
53 /* *INDENT-OFF* */
57 /* *INDENT-ON* */
129 /** M2S Descriptor Prefetch configuration */
136 * prefetch */
155 /** S2M Descriptor Prefetch configuration */
164 al_bool en_pref_prediction; /* enable prefetch prediction */
231 /** M2S DMA Rate Limitation mode */
284 * (in AXI beats-128b) (5b)
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H A Dal_hal_udma_regs_gen.h9 found at http://www.gnu.org/licenses/gpl-2.0.html
77 * Generates interrupt to neighbor DMA
100 /* [0x0] Target-ID control */
102 /* [0x4] TX queue 0/1 Target-ID */
104 /* [0x8] TX queue 2/3 Target-ID */
106 /* [0xc] RX queue 0/1 Target-ID */
108 /* [0x10] RX queue 2/3 Target-ID */
112 /* [0x0] TX queue 0/1 Target-Address */
114 /* [0x4] TX queue 2/3 Target-Address */
116 /* [0x8] RX queue 0/1 Target-Address */
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/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dti,gpmc-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
20 - enum:
21 - ti,am64-nand
22 - ti,omap2-nand
29 - description: Interrupt for fifoevent
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H A Dgpmc-nand.txt7 explained in a separate documents - please refer to
8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
11 Documentation/devicetree/bindings/mtd/nand-controller.yaml
16 - compatible: "ti,omap2-nand"
17 - reg: range id (CS number), base offset and length of the
19 - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
23 - nand-bus-width: Set this numeric value to 16 if the hardware
27 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
28 "sw" 1-bit Hamming ecc code via software
30 "hw-romcode" <deprecated> use "ham1" instead
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/freebsd/sys/contrib/device-tree/src/arm/axis/
H A Dartpec6.dtsi2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
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/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt792x_dma.c1 // SPDX-License-Identifier: ISC
11 #include "dma.h"
18 mt76_wr(dev, dev->irq_map->host_irq_enable, 0); in mt792x_irq_handler()
20 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) in mt792x_irq_handler()
23 tasklet_schedule(&dev->mt76.irq_tasklet); in mt792x_irq_handler()
32 const struct mt792x_irq_map *irq_map = dev->irq_map; in mt792x_irq_tasklet()
35 mt76_wr(dev, irq_map->host_irq_enable, 0); in mt792x_irq_tasklet()
38 intr &= dev->mt76.mmio.irqmask; in mt792x_irq_tasklet()
41 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); in mt792x_irq_tasklet()
43 mask |= intr & (irq_map->rx.data_complete_mask | in mt792x_irq_tasklet()
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7996/
H A Ddma.c1 // SPDX-License-Identifier: ISC
7 #include "../dma.h"
19 mt76_connac_tx_cleanup(&dev->mt76); in mt7996_poll_tx()
30 dev->q_wfdma_mask |= (1 << (q)); \ in mt7996_dma_config()
31 dev->q_int_mask[(q)] = int; \ in mt7996_dma_config()
32 dev->q_id[(q)] = id; \ in mt7996_dma_config()
64 #define PREFETCH(_base, _depth) ((_base) << 16 | (_depth)) in __mt7996_dma_prefetch() macro
65 /* prefetch SRAM wrapping boundary for tx/rx ring. */ in __mt7996_dma_prefetch()
66 mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_FWDL) + ofs, PREFETCH(0x0, 0x2)); in __mt7996_dma_prefetch()
67 mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WM) + ofs, PREFETCH(0x20, 0x2)); in __mt7996_dma_prefetch()
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dti,gpmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controller
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H A Domap-gpmc.txt7 - compatible: Should be set to one of the following:
9 ti,omap2420-gpmc (omap2420)
10 ti,omap2430-gpmc (omap2430)
11 ti,omap3430-gpmc (omap3430 & omap3630)
12 ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
13 ti,am3352-gpmc (am335x devices)
15 - reg: A resource specifier for the register space
17 - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
19 - #address-cells: Must be set to 2 to allow memory address translation
20 - #size-cells: Must be set to 1 to allow CS address passing
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Ddma.c1 // SPDX-License-Identifier: ISC
5 #include "../dma.h"
11 struct mt7915_dev *dev = phy->dev; in mt7915_init_tx_queues()
13 if (mtk_wed_device_active(&phy->dev->mt76.mmio.wed)) { in mt7915_init_tx_queues()
14 if (is_mt798x(&dev->mt76)) in mt7915_init_tx_queues()
19 idx -= MT_TXQ_ID(0); in mt7915_init_tx_queues()
22 return mt76_connac_init_tx_queues(phy->mt76, idx, n_desc, ring_base, in mt7915_init_tx_queues()
32 mt76_connac_tx_cleanup(&dev->mt76); in mt7915_poll_tx()
43 dev->wfdma_mask |= (1 << (q)); \ in mt7915_dma_config()
44 dev->q_int_mask[(q)] = int; \ in mt7915_dma_config()
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/freebsd/sys/contrib/ncsw/inc/flib/
H A Dfsl_fman_port.h2 * Copyright 2008-2013 Freescale Semiconductor Inc.
154 uint32_t fmbm_rda; /**< Rx DMA attributes*/
175 uint32_t reserved0074[0x2]; /**< (0x074-0x07C) */
179 /**< Buffer Manager pool Information-*/
181 /**< Allocate Counter-*/
183 /**< 0x130/0x140 - 0x15F reserved -*/
194 uint32_t fmbm_rfldec; /**< Rx Frames List DMA Error Counter*/
203 uint32_t fmbm_rduc; /**< Rx DMA Utilization Counter*/
207 uint32_t fmbm_rdbg; /**< Rx Debug-*/
214 uint32_t fmbm_tda; /**< Tx DMA attributes */
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dl2c2x0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
33 - enum:
34 - arm,pl310-cache
35 - arm,l220-cache
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/freebsd/sys/contrib/device-tree/Bindings/cache/
H A Dl2c2x0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
33 - enum:
34 - arm,pl310-cache
35 - arm,l220-cache
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/freebsd/sys/contrib/device-tree/Bindings/iommu/
H A Darm,smmu-v3.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
15 revisions, replacing the MMIO register interface with in-memory command
21 pattern: "^iommu@[0-9a-f]*"
23 const: arm,smmu-v3
32 interrupt-names:
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/freebsd/share/man/man4/
H A Dahc.437 .Bd -ragged -offset indent
48 .Bd -literal -offset indent
64 .Tn SCSI-Select
72 For systems that store non-volatile settings in a system specific manner
78 many chip-down motherboard configurations.
88 .Bd -ragged -offset indent
89 .Bl -column "aic7895CX" "MIPSX" "PCI/64X" "MaxSyncX" "MaxWidthX" "SCBsX" "2 3 4 5 6 7 8X"
106 .Bl -enum -compact
108 Multiplexed Twin Channel Device - One controller servicing two busses.
110 Multi-function Twin Channel Device - Two controllers on one chip.
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H A Dioat.434 .Bd -ragged -offset indent
40 .Bd -literal -offset indent
142 driver provides a kernel API to a variety of DMA engines on some Intel server
145 There is a number of DMA channels per CPU package.
150 Blockfill operations can be used to write a 64-bit pattern to memory.
152 Copy operations can be used to offload memory copies to the DMA engines.
167 Software can control this on a per-channel basis with the
177 All operations are safe to use in a non-blocking context with the
186 For example, such a scenario can happen when two related DMA operations are
188 First, a DMA copy to one location (A), followed directly by a DMA copy
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/freebsd/sys/net/
H A Diflib.c1 /*-
2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
107 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
108 * we prefetch needs to be determined by the time spent in m_free vis a vis
109 * the cost of a prefetch. This will of course vary based on the workload:
110 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
111 * is quite expensive, thus suggesting very little prefetch.
112 * - small packet forwarding which is just returning a single mbuf to
119 * - private structures
120 * - iflib private utility functions
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/freebsd/sys/dev/bhnd/cores/pci/
H A Dbhnd_pcireg.h1 /*-
2 * SPDX-License-Identifier: ISC
29 * PCI/PCIe-Gen1 DMA Constants
35 #define BHND_PCIE_DMA32_TRANSLATION 0x80000000 /**< PCIe-Gen1 DMA32 address translation (sb2pcitr…
36 #define BHND_PCIE_DMA32_MASK BHND_PCIE_SBTOPCI2_MASK /**< PCIe-Gen1 DMA32 translation mask */
38 #define BHND_PCIE_DMA64_TRANSLATION _BHND_PCIE_DMA64(TRANSLATION) /**< PCIe-Gen1 DMA64 address tran…
39 #define BHND_PCIE_DMA64_MASK _BHND_PCIE_DMA64(MASK) /**< PCIe-Gen1 DMA64 translation mask */
76 /* BHND_PCI_ARB_CTL - ParkID (>= rev8) */
122 #define BHND_PCI_SBTOPCI_PREF 0x4 /* prefetch enable */
138 * PCIe-Gen1 Core Registers
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/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-metho
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/freebsd/sys/dev/aic7xxx/
H A Daic7xxx.seq1 /*-
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2001 Adaptec Inc.
19 * 3. Neither the names of the above-listed copyright holders nor the names
58 * use byte 27 of the SCB as a pseudo-next pointer and to thread a list
59 * of SCBs that are awaiting selection. Since 0-0xfe are valid SCB indexes,
61 * this list every time a request sense occurs or after completing a non-tagged
76 if ((ahc->features & AHC_ULTRA2) != 0) {
80 if ((ahc->features & AHC_TWIN) != 0) {
88 if ((ahc->features & AHC_TWIN) != 0) {
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/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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/freebsd/sys/contrib/ena-com/
H A Dena_plat.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2015-2023 Amazon.com, Inc. or its affiliates.
139 const __typeof(((type *)0)->member) *__p = (ptr); \
140 (type *)((uintptr_t)__p - offsetof(type, member)); \
144 ena_log((ctx)->dmadev, level, "%s() [TID:%d]: " \
145 fmt, __func__, curthread->td_tid, ##args)
187 #define GENMASK(h, l) (((~0U) - (1U << (l)) + 1) & (~0U >> (32 - 1 - (h))))
188 #define GENMASK_ULL(h, l) (((~0ULL) << (l)) & (~0ULL >> (64 - 1 - (h))))
202 #define ENA_COM_TRY_AGAIN -1
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/freebsd/sys/dev/malo/
H A Dif_malo.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
245 uint16_t action; /* 0 -> unset, 1 -> set */
351 * DMA state for tx/rx descriptors.
356 * allocated using the bus dma api.
365 bus_dma_tag_t dd_dmat; /* bus DMA tag */
366 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */
374 * because f/w prefetch's the next descriptor linearly
407 uint16_t pad; /* align to 4-byte boundary */
411 bus_dmamap_sync((txq)->dma.dd_dmat, (txq)->dma.dd_dmamap, how); \
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