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/linux/Documentation/devicetree/bindings/leds/backlight/
H A Dpwm-backlight.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/leds/backlight/pwm-backlight.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: pwm-backlight
10 - Lee Jones <lee@kernel.org>
11 - Daniel Thompson <daniel.thompson@linaro.org>
12 - Jingoo Han <jingoohan1@gmail.com>
15 - $ref: common.yaml#
19 const: pwm-backlight
[all …]
/linux/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_83xx_init.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2009-2013 QLogic Corporation
74 u16 delay; member
78 u16 delay;
136 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); in qlcnic_83xx_idc_check_driver_presence_reg()
146 cur = adapter->ahw->idc.curr_state; in qlcnic_83xx_idc_log_state_history()
147 prev = adapter->ahw->idc.prev_state; in qlcnic_83xx_idc_log_state_history()
149 dev_info(&adapter->pdev->dev, in qlcnic_83xx_idc_log_state_history()
151 adapter->ahw->idc.name[cur], in qlcnic_83xx_idc_log_state_history()
152 adapter->ahw->idc.name[prev]); in qlcnic_83xx_idc_log_state_history()
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/linux/drivers/spi/
H A Dspi-imx.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
9 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
30 #include <linux/dma/imx-dma.h>
138 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
143 return d->devtype_data->devtype == IMX35_CSPI; in is_imx35_cspi()
148 return d->devtype_data->devtype == IMX51_ECSPI; in is_imx51_ecspi()
153 return d->devtype_data->devtype == IMX53_ECSPI; in is_imx53_ecspi()
159 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
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/linux/drivers/gpu/drm/i915/gt/
H A Dgen6_engine_cs.c1 // SPDX-License-Identifier: MIT
18 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
22 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
23 * produced by non-pipelined state commands), software needs to first
24 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
27 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
28 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
32 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
33 * BEFORE the pipe-control with a post-sync op and no write-cache
41 * - Render Target Cache Flush Enable ([12] of DW1)
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/linux/arch/arm64/boot/dts/qcom/
H A Dsc7280-crd-r3.dts1 // SPDX-License-Identifier: BSD-3-Clause
8 /dts-v1/;
10 #include "sc7280-idp.dtsi"
11 #include "sc7280-idp-ec-h1.dtsi"
14 model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4)";
15 compatible = "qcom,sc7280-crd",
16 "google,hoglin-rev3", "google,hoglin-rev4",
17 "google,piglin-rev3", "google,piglin-rev4",
25 stdout-path = "serial0:115200n8";
30 regulators-2 {
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H A Dsc7280-herobrine-crd.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "sc7280-herobrine.dtsi"
11 #include "sc7280-herobrine-audio-wcd9385.dtsi"
12 #include "sc7280-herobrine-lte-sku.dtsi"
27 vreg_edp_bl_crd: vreg-edp-bl-crd-regulator {
28 compatible = "regulator-fixed";
29 regulator-name = "vreg_edp_bl_crd";
32 enable-active-high;
33 pinctrl-names = "default";
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/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-pwrseq-simple.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
19 const: mmc-pwrseq-simple
21 reset-gpios:
28 They will be de-asserted right after the power has been provided to the
33 description: Handle for the entry in clock-names.
35 clock-names:
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/linux/drivers/clk/tegra/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dmdio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
17 bus. These should follow the generic ethernet-phy.yaml document, or
22 pattern: '^mdio(-(bus|external))?(@.+|-([0-9]+))?$'
24 "#address-cells":
27 "#size-cells":
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H A Drenesas,ethertsn.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Ethernet TSN End-station
10 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
14 Gbps full-duplex link via MII/GMII/RMII/RGMII. Depending on the connected PHY.
17 - $ref: ethernet-controller.yaml#
22 - enum:
23 - renesas,r8a779g0-ethertsn # R-Car V4H
24 - const: renesas,rcar-gen4-ethertsn
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H A Dhisilicon-femac.txt4 - compatible: should contain one of the following version strings:
5 * "hisilicon,hisi-femac-v1"
6 * "hisilicon,hisi-femac-v2"
7 and the soc string "hisilicon,hi3516cv300-femac".
8 - reg: specifies base physical address(s) and size of the device registers.
11 - interrupts: should contain the MAC interrupt.
12 - clocks: A phandle to the MAC main clock.
13 - resets: should contain the phandle to the MAC reset signal(required) and
15 - reset-names: should contain the reset signal name "mac"(required)
17 - phy-mode: see ethernet.txt [1].
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/linux/tools/power/pm-graph/config/
H A Dsuspend-x2-proc.cfg2 # Proc S3 (Suspend to Mem) x2 test - includes user processes
9 # sudo ./sleepgraph.py -config config/suspend-proc.cfg
14 # ---- General Options ----
26 output-dir: suspend-{hostname}-{date}-{time}-x2-proc
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
[all …]
H A Dfreeze-dev.cfg2 # Dev S2 (Freeze) test - includes src calls / kernel threads
9 # sudo ./sleepgraph.py -config config/freeze-dev.cfg
14 # ---- General Options ----
26 output-dir: freeze-{hostname}-{date}-{time}-dev
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
[all …]
H A Dstandby-dev.cfg2 # Dev S1 (Standby) test - includes src calls / kernel threads
9 # sudo ./sleepgraph.py -config config/standby-dev.cfg
14 # ---- General Options ----
26 output-dir: standby-{hostname}-{date}-{time}-dev
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
[all …]
H A Dsuspend-dev.cfg2 # Dev S3 (Suspend to Mem) test - includes src calls / kernel threads
9 # sudo ./sleepgraph.py -config config/suspend-dev.cfg
14 # ---- General Options ----
26 output-dir: suspend-{hostname}-{date}-{time}-dev
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
[all …]
H A Dstandby-callgraph.cfg9 # sudo ./sleepgraph.py -config config/standby-callgraph.cfg
15 # ---- General Options ----
27 output-dir: standby-{hostname}-{date}-{time}-cg
41 # ---- Advanced Options ----
58 # Back to Back Suspend Delay
59 # Time delay between the two test runs in ms (default: 0 ms)
62 # Pre Suspend Delay
63 # Include an N ms delay before (1st) suspend (default: 0 ms)
66 # Post Resume Delay
67 # Include an N ms delay after (last) resume (default: 0 ms)
[all …]
H A Dfreeze-callgraph.cfg9 # sudo ./sleepgraph.py -config config/freeze-callgraph.cfg
15 # ---- General Options ----
27 output-dir: freeze-{hostname}-{date}-{time}-cg
41 # ---- Advanced Options ----
58 # Back to Back Suspend Delay
59 # Time delay between the two test runs in ms (default: 0 ms)
62 # Pre Suspend Delay
63 # Include an N ms delay before (1st) suspend (default: 0 ms)
66 # Post Resume Delay
67 # Include an N ms delay after (last) resume (default: 0 ms)
[all …]
H A Dfreeze.cfg9 # sudo ./sleepgraph.py -config config/freeze.cfg
14 # ---- General Options ----
26 output-dir: freeze-{hostname}-{date}-{time}
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
66 # Include an N ms delay after (last) resume (default: 0 ms)
[all …]
H A Dstandby.cfg9 # sudo ./sleepgraph.py -config config/standby.cfg
14 # ---- General Options ----
26 output-dir: standby-{hostname}-{date}-{time}
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
66 # Include an N ms delay after (last) resume (default: 0 ms)
[all …]
H A Dsuspend.cfg9 # sudo ./sleepgraph.py -config config/suspend.cfg
14 # ---- General Options ----
26 output-dir: suspend-{hostname}-{date}-{time}
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
66 # Include an N ms delay after (last) resume (default: 0 ms)
[all …]
H A Dsuspend-callgraph.cfg9 # sudo ./sleepgraph.py -config config/suspend.cfg
15 # ---- General Options ----
27 output-dir: suspend-{hostname}-{date}-{time}-cg
41 # ---- Advanced Options ----
58 # Back to Back Suspend Delay
59 # Time delay between the two test runs in ms (default: 0 ms)
62 # Pre Suspend Delay
63 # Include an N ms delay before (1st) suspend (default: 0 ms)
66 # Post Resume Delay
67 # Include an N ms delay after (last) resume (default: 0 ms)
[all …]
/linux/drivers/net/ethernet/emulex/benet/
H A Dbe_hw.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2005-2016 Broadcom.
7 * linux-drivers@emulex.com
16 * The software must write this register twice to post any command. First,
33 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
42 /* MPU semphore POST stage values */
44 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
46 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
127 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
128 #define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx93-var-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
12 model = "Variscite VAR-SOM-MX93 module";
13 compatible = "variscite,var-som-mx93", "fsl,imx93";
15 mmc_pwrseq: mmc-pwrseq {
16 compatible = "mmc-pwrseq-simple";
17 post-power-on-delay-ms = <100>;
18 power-off-delay-us = <10000>;
19 reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
25 pinctrl-names = "default";
[all …]
H A Dimx93-phyboard-segin-peb-wlbt-05.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include "imx93-pinfunc.h"
14 usdhc3_pwrseq: usdhc3-pwrseq {
15 compatible = "mmc-pwrseq-simple";
16 post-power-on-delay-ms = <100>;
17 power-off-delay-us = <60>;
18 reset-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
23 pinctrl-names = "default";
[all …]
/linux/drivers/scsi/aacraid/
H A Drx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Copyright (c) 2000-2010 Adaptec, Inc.
10 * 2010-2015 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
11 * 2016-2017 Microsemi Corp. (aacraid@microsemi.com)
25 #include <linux/delay.h>
46 if (likely(intstat & ~(dev->OIMR))) { in aac_rx_intr_producer()
49 aac_printf(dev, readl (&dev->IndexRegs->Mailbox[5])); in aac_rx_intr_producer()
55 aac_command_normal(&dev->queues->queue[HostNormCmdQueue]); in aac_rx_intr_producer()
59 aac_response_normal(&dev->queues->queue[HostNormRespQueue]); in aac_rx_intr_producer()
113 * aac_rx_disable_interrupt - Disable interrupts
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