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/linux/Documentation/devicetree/bindings/leds/backlight/
H A Dpwm-backlight.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/leds/backlight/pwm-backlight.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: pwm-backlight
10 - Lee Jones <lee@kernel.org>
11 - Daniel Thompson <daniel.thompson@linaro.org>
12 - Jingoo Han <jingoohan1@gmail.com>
15 - $ref: common.yaml#
19 const: pwm-backlight
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dfsl,fec.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Wei Fang <wei.fang@nxp.com>
12 - NXP Linux Team <linux-imx@nxp.com>
15 - $ref: ethernet-controller.yaml#
20 - enum:
21 - fsl,imx25-fec
22 - fsl,imx27-fec
[all …]
H A Dmdio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
17 bus. These should follow the generic ethernet-phy.yaml document, or
22 pattern: '^mdio(-(bus|external))?(@.+|-([0-9]+))?$'
24 "#address-cells":
27 "#size-cells":
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/linux/drivers/mmc/core/
H A Dcore.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <linux/delay.h>
76 void _mmc_detect_change(struct mmc_host *host, unsigned long delay,
141 * mmc_claim_host - exclusively claim a host
156 * mmc_pre_req - Prepare for a new request
166 if (host->ops->pre_req) in mmc_pre_req()
167 host->ops->pre_req(host, mrq); in mmc_pre_req()
171 * mmc_post_req - Post process a completed request
172 * @host: MMC host to post process command
173 * @mrq: MMC request to post process for
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/linux/drivers/gpu/drm/ci/
H A Dgitlab-ci.yml2 DRM_CI_PROJECT_PATH: &drm-ci-project-path mesa/mesa
3 DRM_CI_COMMIT_SHA: &drm-ci-commit-sha d9849ac46623797a9f56fb9d46dc52460ac477de
6 TARGET_BRANCH: drm-next
10 DEQP_RUNNER_GIT_URL: https://gitlab.freedesktop.org/mesa/deqp-runner.git
13 FDO_UPSTREAM_REPO: helen.fornazier/linux # The repo where the git-archive daily runs
14 MESA_TEMPLATES_COMMIT: &ci-templates-commit d5aa3941aa03c2f716595116354fb81eb8012acb
16 CI_PRE_CLONE_SCRIPT: |-
17 set -o xtrace
18 …-L --retry 4 -f --retry-all-errors --retry-delay 60 -s ${DRM_CI_PROJECT_URL}/-/raw/${DRM_CI_COMMIT…
19 bash download-git-cache.sh
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/linux/arch/arm64/boot/dts/renesas/
H A Dwhite-hawk-ethernet.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the White Hawk RAVB/Ethernet(1000Base-T1)
4 * sub-board
17 pinctrl-0 = <&avb1_pins>;
18 pinctrl-names = "default";
19 phy-handle = <&avb1_phy>;
23 #address-cells = <1>;
24 #size-cells = <0>;
26 reset-gpios = <&gpio6 1 GPIO_ACTIVE_LOW>;
27 reset-post-delay-us = <4000>;
[all …]
/linux/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_83xx_init.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2009-2013 QLogic Corporation
74 u16 delay; member
78 u16 delay;
136 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); in qlcnic_83xx_idc_check_driver_presence_reg()
146 cur = adapter->ahw->idc.curr_state; in qlcnic_83xx_idc_log_state_history()
147 prev = adapter->ahw->idc.prev_state; in qlcnic_83xx_idc_log_state_history()
149 dev_info(&adapter->pdev->dev, in qlcnic_83xx_idc_log_state_history()
151 adapter->ahw->idc.name[cur], in qlcnic_83xx_idc_log_state_history()
152 adapter->ahw->idc.name[prev]); in qlcnic_83xx_idc_log_state_history()
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/linux/drivers/gpu/drm/i915/gt/
H A Dgen6_engine_cs.c1 // SPDX-License-Identifier: MIT
18 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
22 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
23 * produced by non-pipelined state commands), software needs to first
24 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
27 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
28 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
32 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
33 * BEFORE the pipe-control with a post-sync op and no write-cache
41 * - Render Target Cache Flush Enable ([12] of DW1)
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsc7280-crd-r3.dts1 // SPDX-License-Identifier: BSD-3-Clause
8 /dts-v1/;
10 #include "sc7280-idp.dtsi"
11 #include "sc7280-idp-ec-h1.dtsi"
14 model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4)";
15 compatible = "qcom,sc7280-crd",
16 "google,hoglin-rev3", "google,hoglin-rev4",
17 "google,piglin-rev3", "google,piglin-rev4",
25 stdout-path = "serial0:115200n8";
30 regulators-2 {
[all …]
/linux/drivers/hid/i2c-hid/
H A Di2c-hid-of.c12 * Copyright (c) 2000-2005 Vojtech Pavlik <vojtech@suse.cz>
13 * Copyright (c) 2005 Michael Haboustak <mike-@cinci.rr.com> for Concept2, Inc
14 * Copyright (c) 2007-2008 Oliver Neukum
15 * Copyright (c) 2006-2010 Jiri Kosina
22 #include <linux/delay.h>
33 #include "i2c-hid.h"
48 struct device *dev = &ihid_of->client->dev; in i2c_hid_of_power_up()
51 ret = regulator_bulk_enable(ARRAY_SIZE(ihid_of->supplies), in i2c_hid_of_power_up()
52 ihid_of->supplies); in i2c_hid_of_power_up()
58 if (ihid_of->post_power_delay_ms) in i2c_hid_of_power_up()
[all …]
/linux/drivers/spi/
H A Dspi-imx.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
8 #include <linux/delay.h>
10 #include <linux/dma-mapping.h>
26 #include <linux/dma/imx-dma.h>
133 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
138 return d->devtype_data->devtype == IMX35_CSPI; in is_imx35_cspi()
143 return d->devtype_data->devtype == IMX51_ECSPI; in is_imx51_ecspi()
148 return d->devtype_data->devtype == IMX53_ECSPI; in is_imx53_ecspi()
154 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-pwrseq-simple.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
19 const: mmc-pwrseq-simple
21 reset-gpios:
28 They will be de-asserted right after the power has been provided to the
33 description: Handle for the entry in clock-names.
35 clock-names:
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/linux/drivers/clk/tegra/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
[all …]
/linux/tools/power/pm-graph/config/
H A Dsuspend-x2-proc.cfg2 # Proc S3 (Suspend to Mem) x2 test - includes user processes
9 # sudo ./sleepgraph.py -config config/suspend-proc.cfg
14 # ---- General Options ----
26 output-dir: suspend-{hostname}-{date}-{time}-x2-proc
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
[all …]
H A Dfreeze-dev.cfg2 # Dev S2 (Freeze) test - includes src calls / kernel threads
9 # sudo ./sleepgraph.py -config config/freeze-dev.cfg
14 # ---- General Options ----
26 output-dir: freeze-{hostname}-{date}-{time}-dev
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
[all …]
H A Dstandby-dev.cfg2 # Dev S1 (Standby) test - includes src calls / kernel threads
9 # sudo ./sleepgraph.py -config config/standby-dev.cfg
14 # ---- General Options ----
26 output-dir: standby-{hostname}-{date}-{time}-dev
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
[all …]
H A Dsuspend-dev.cfg2 # Dev S3 (Suspend to Mem) test - includes src calls / kernel threads
9 # sudo ./sleepgraph.py -config config/suspend-dev.cfg
14 # ---- General Options ----
26 output-dir: suspend-{hostname}-{date}-{time}-dev
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
[all …]
H A Dstandby-callgraph.cfg9 # sudo ./sleepgraph.py -config config/standby-callgraph.cfg
15 # ---- General Options ----
27 output-dir: standby-{hostname}-{date}-{time}-cg
41 # ---- Advanced Options ----
58 # Back to Back Suspend Delay
59 # Time delay between the two test runs in ms (default: 0 ms)
62 # Pre Suspend Delay
63 # Include an N ms delay before (1st) suspend (default: 0 ms)
66 # Post Resume Delay
67 # Include an N ms delay after (last) resume (default: 0 ms)
[all …]
H A Dfreeze-callgraph.cfg9 # sudo ./sleepgraph.py -config config/freeze-callgraph.cfg
15 # ---- General Options ----
27 output-dir: freeze-{hostname}-{date}-{time}-cg
41 # ---- Advanced Options ----
58 # Back to Back Suspend Delay
59 # Time delay between the two test runs in ms (default: 0 ms)
62 # Pre Suspend Delay
63 # Include an N ms delay before (1st) suspend (default: 0 ms)
66 # Post Resume Delay
67 # Include an N ms delay after (last) resume (default: 0 ms)
[all …]
H A Dfreeze.cfg9 # sudo ./sleepgraph.py -config config/freeze.cfg
14 # ---- General Options ----
26 output-dir: freeze-{hostname}-{date}-{time}
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
66 # Include an N ms delay after (last) resume (default: 0 ms)
[all …]
H A Dstandby.cfg9 # sudo ./sleepgraph.py -config config/standby.cfg
14 # ---- General Options ----
26 output-dir: standby-{hostname}-{date}-{time}
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
66 # Include an N ms delay after (last) resume (default: 0 ms)
[all …]
H A Dsuspend.cfg9 # sudo ./sleepgraph.py -config config/suspend.cfg
14 # ---- General Options ----
26 output-dir: suspend-{hostname}-{date}-{time}
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
66 # Include an N ms delay after (last) resume (default: 0 ms)
[all …]
H A Dsuspend-callgraph.cfg9 # sudo ./sleepgraph.py -config config/suspend.cfg
15 # ---- General Options ----
27 output-dir: suspend-{hostname}-{date}-{time}-cg
41 # ---- Advanced Options ----
58 # Back to Back Suspend Delay
59 # Time delay between the two test runs in ms (default: 0 ms)
62 # Pre Suspend Delay
63 # Include an N ms delay before (1st) suspend (default: 0 ms)
66 # Post Resume Delay
67 # Include an N ms delay after (last) resume (default: 0 ms)
[all …]
/linux/drivers/net/ethernet/emulex/benet/
H A Dbe_hw.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2005-2016 Broadcom.
7 * linux-drivers@emulex.com
16 * The software must write this register twice to post any command. First,
33 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
42 /* MPU semphore POST stage values */
44 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
46 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
127 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
128 #define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx93-var-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
12 model = "Variscite VAR-SOM-MX93 module";
13 compatible = "variscite,var-som-mx93", "fsl,imx93";
15 mmc_pwrseq: mmc-pwrseq {
16 compatible = "mmc-pwrseq-simple";
17 post-power-on-delay-ms = <100>;
18 power-off-delay-us = <10000>;
19 reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
23 reg_eqos_phy: regulator-eqos-phy {
[all …]

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