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/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dtvp7002.txt7 - compatible : Must be "ti,tvp7002"
10 - hsync-active: HSYNC Polarity configuration for the bus. Default value when
13 - vsync-active: VSYNC Polarity configuration for the bus. Default value when
16 - pclk-sample: Clock polarity of the bus. Default value when this property is
19 - sync-on-green-active: Active state of Sync-on-green signal property of the
21 0 = Normal Operation (Active Low, Default)
24 - field-even-active: Active-high Field ID output polarity control of the bus.
27 0 = Normal Operation (Active Low, Default)
28 1 = FID output polarity inverted
31 video-interfaces.txt.
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H A Dadv7604.txt12 - compatible: Must contain one of the following
13 - "adi,adv7611" for the ADV7611
14 - "adi,adv7612" for the ADV7612
16 - reg: I2C slave addresses
17 The ADV76xx has up to thirteen 256-byte maps that can be accessed via the
22 - hpd-gpios: References to the GPIOs that control the HDMI hot-plug
23 detection pins, one per HDMI input. The active flag indicates the GPIO
24 level that enables hot-plug detection.
28 Documentation/devicetree/bindings/media/video-interfaces.txt. The port nodes
32 ------------------------------------------------------------
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H A Dov5645.txt1 * Omnivision 1/4-Inch 5Mp CMOS Digital Image Sensor
3 The Omnivision OV5645 is a 1/4-Inch CMOS active pixel digital image sensor with
4 an active array size of 2592H x 1944V. It is programmable through a serial I2C
8 - compatible: Value should be "ovti,ov5645".
9 - clocks: Reference to the xclk clock.
10 - clock-names: Should be "xclk".
11 - clock-frequency: Frequency of the xclk clock.
12 - enable-gpios: Chip enable GPIO. Polarity is GPIO_ACTIVE_HIGH. This corresponds
13 to the hardware pin PWDNB which is physically active low.
14 - reset-gpios: Chip reset GPIO. Polarity is GPIO_ACTIVE_LOW. This corresponds to
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H A Dst,st-mipid02.txt1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
8 polarity swap. First port also supports data lane swap.
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
17 - VDDE-supply: sensor digital IO supply. Must be 1.8 volts.
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/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio.txt5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
39 such as if the consumer desire the line to be active low (inverted) or open
44 recommended to use the two-cell approach.
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H A Dgpio-vf610.txt8 - compatible : Should be "fsl,<soc>-gpio", below is supported list:
9 "fsl,vf610-gpio"
10 "fsl,imx7ulp-gpio"
11 - reg : The first reg tuple represents the PORT module, the second tuple
13 - interrupts : Should be the port interrupt shared by all 32 pins.
14 - gpio-controller : Marks the device node as a gpio controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and
16 the second cell is used to specify the gpio polarity:
17 0 = active high
18 1 = active low
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H A Dnvidia,tegra20-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-gpio
18 - nvidia,tegra30-gpio
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H A Dbrcm,brcmstb-gpio.txt3 The controller's registers are organized as sets of eight 32-bit
9 - compatible:
10 Must be "brcm,brcmstb-gpio"
12 - reg:
16 - #gpio-cells:
19 bit[0]: polarity (0 for active-high, 1 for active-low)
21 - gpio-controller:
24 - brcm,gpio-bank-widths:
30 - interrupts:
33 - interrupts-extended:
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H A Dnvidia,tegra20-gpio.txt4 - compatible : "nvidia,tegra<chip>-gpio"
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller. For Tegra20,
9 - #gpio-cells : Should be two. The first cell is the pin number and the
11 - bit 0 specifies polarity (0 for normal, 1 for inverted)
12 - gpio-controller : Marks the device node as a GPIO controller.
13 - #interrupt-cells : Should be 2.
17 1 = low-to-high edge triggered.
18 2 = high-to-low edge triggered.
19 4 = active high level-sensitive.
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/freebsd/sys/contrib/device-tree/Bindings/display/panel/
H A Dpanel-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Lauren
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/freebsd/share/man/man4/
H A Dlm75.451 .Bd -literal
62 dev.lm75.0.polarity: active-low
65 .Bl -tag -width ".Va dev.lm75.%d.temperature"
67 Is the read-only value of the current temperature read by the sensor.
84 .It Va dev.lm75.%d.polarity
85 Sets the polarity of the sensor interrupt pin.
86 It can be set to 'active-low' (default) or 'active-high'.
87 Please note that the output pin is an open-drain output and it needs a
88 proper pull-up resistor to work.
92 active, i.e., it can be woken up by setting this option to '0' again.
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/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Drichtek,rtmv20-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
27 wakeup-sourc
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H A Dgpio-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/gpio-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Girdwood <lgirdwood@gmail.com>
11 - Mark Brown <broonie@kernel.org>
18 - $ref: regulator.yaml#
22 const: regulator-gpio
24 regulator-name: true
26 enable-gpios:
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/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dci-hdrc-usb2.txt4 - compatible: should be one of:
5 "fsl,imx23-usb"
6 "fsl,imx27-usb"
7 "fsl,imx28-usb"
8 "fsl,imx6q-usb"
9 "fsl,imx6sl-usb"
10 "fsl,imx6sx-usb"
11 "fsl,imx6ul-usb"
12 "fsl,imx7d-usb"
13 "fsl,imx7ulp-usb"
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H A Dfsl,imx8mp-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc
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H A Dchipidea,usb2-imx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
15 - enum:
16 - fsl,imx27-usb
17 - items:
18 - enum:
19 - fsl,imx23-usb
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/freebsd/sys/contrib/device-tree/include/dt-bindings/sound/
H A Dcs35l45.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * cs35l45.h -- CS35L45 ALSA SoC audio driver DT bindings header
12 * cirrus,asp-sdout-hiz-ctrl
14 * TX_HIZ_UNUSED: TX pin high-impedance during unused slots.
15 * TX_HIZ_DISABLED: TX pin high-impedance when all channels disabled.
21 * Optional GPIOX Sub-nodes:
22 * The cs35l45 node can have up to three "cirrus,gpio-ctrlX" ('X' = [1,2,3])
23 * sub-nodes for configuring the GPIO pins.
25 * - gpio-dir : GPIO pin direction. Valid only when 'gpio-ctrl'
30 * - gpio-lvl : GPIO level. Valid only when 'gpio-ctrl' is 1 and 'gpio-dir' is 0.
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/freebsd/sys/contrib/device-tree/Bindings/hwmon/
H A Dti,ina2xx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 The INA209 is a high-side current shunt and power monitor with
23 - ti,ina209
24 - ti,ina219
25 - ti,ina220
26 - ti,ina226
27 - ti,ina230
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/freebsd/sys/contrib/device-tree/Bindings/serial/
H A Dnxp,sc16is7xx.txt1 * NXP SC16IS7xx advanced Universal Asynchronous Receiver-Transmitter (UART)
5 - compatible: Should be one of the following:
6 - "nxp,sc16is740" for NXP SC16IS740,
7 - "nxp,sc16is741" for NXP SC16IS741,
8 - "nxp,sc16is750" for NXP SC16IS750,
9 - "nxp,sc16is752" for NXP SC16IS752,
10 - "nxp,sc16is760" for NXP SC16IS760,
11 - "nxp,sc16is762" for NXP SC16IS762.
12 - reg: I2C address of the SC16IS7xx device.
13 - interrupt
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H A Drs485.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 direction for the built-in half-duplex mode. The properties described
11 hereafter shall be given to a half-duple
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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_serdes_internal_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
48 * 0 - Hard reset is asserted
49 * 1 - Hard reset is de-asserted
58 * 0 - Hard reset is taken from the interface pins
59 * 1 - Hard reset is taken from registers
121 * PMA serial RX-to-TX loop-back enable (from AGC to IO Driver). Serial receive
122 * to transmit loopback: 0 - Disables loopback 1 - Transmits the untimed,
129 * PMA TX-to-RX buffered serial loop-back enable (bypasses IO Driver). Serial
130 * transmit to receive buffered loopback: 0 - Disables loopback 1 - Loops back
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H A Dal_hal_serdes_hssp_internal_regs.h9 found at http://www.gnu.org/licenses/gpl-2.0.html
47 * 0 - Hard reset is asserted
48 * 1 - Hard reset is de-asserted
57 * 0 - Hard reset is taken from the interface pins
58 * 1 - Hard reset is taken from registers
120 * PMA serial RX-to-TX loop-back enable (from AGC to IO Driver). Serial receive
121 * to transmit loopback: 0 - Disables loopback 1 - Transmits the untimed,
128 * PMA TX-to-RX buffered serial loop-back enable (bypasses IO Driver). Serial
129 * transmit to receive buffered loopback: 0 - Disables loopback 1 - Loops back
136 * PMA TX-to-RX I/O serial loop-back enable (loop back done directly from TX to
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/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dnau8821.txt6 - compatible : Must be "nuvoton,nau8821"
8 - reg : the I2C address of the device. This is either 0x1B (CSB=0) or 0x54 (CSB=1).
11 - nuvoton,jkdet-enable: Enable jack detection via JKDET pin.
12 - nuvoton,jkdet-pull-enable: Enable JKDET pin pull. If set - pin pull enabled,
14 - nuvoton,jkdet-pull-up: Pull-up JKDET pin. If set then JKDET pin is pull up, otherwise pull down.
15 - nuvoton,jkdet-polarity: JKDET pin polarity. 0 - active high, 1 - active low.
17 - nuvoton,vref-impedance: VREF Impedance selection
18 0 - Open
19 1 - 25 kOhm
20 2 - 125 kOhm
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/freebsd/sys/contrib/device-tree/Bindings/display/exynos/
H A Dexynos_dp.txt5 -dp-controller node
6 -dptx-phy node(defined inside dp-controller node)
8 For the DP-PHY initialization, we use the dptx-phy node.
9 Required properties for dptx-phy: deprecated, use phys and phy-names
10 -reg: deprecated
12 -samsung,enable-mask: deprecated
13 The bit-mask used to enable/disable DP PHY.
15 For the Panel initialization, we read data from dp-controller node.
16 Required properties for dp-controller:
17 -compatible:
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/freebsd/sys/x86/acpica/
H A Dmadt.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
109 return (-50); in madt_probe()
120 madt_length = madt->Header.Length; in madt_probe_cpus()
121 KASSERT(madt != NULL, ("Unable to re-map MADT")); in madt_probe_cpus()
154 if ((dmartbl->Flags & ACPI_DMAR_X2APIC_OPT_OUT) != 0) in madt_x2apic_disable_reason()
174 * It seems that some SandyBridge-based notebook in madt_x2apic_disable_reason()
247 lapic_init(madt->Address); in madt_setup_local()
249 (int)sizeof(madt->Header.OemId), madt->Header.OemId, in madt_setup_local()
250 (int)sizeof(madt->Header.OemTableId), madt->Header.OemTableId); in madt_setup_local()
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