1d5b0e70fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2d5b0e70fSEmmanuel Vadot /* 3d5b0e70fSEmmanuel Vadot * cs35l45.h -- CS35L45 ALSA SoC audio driver DT bindings header 4d5b0e70fSEmmanuel Vadot * 5d5b0e70fSEmmanuel Vadot * Copyright 2022 Cirrus Logic, Inc. 6d5b0e70fSEmmanuel Vadot */ 7d5b0e70fSEmmanuel Vadot 8d5b0e70fSEmmanuel Vadot #ifndef DT_CS35L45_H 9d5b0e70fSEmmanuel Vadot #define DT_CS35L45_H 10d5b0e70fSEmmanuel Vadot 11d5b0e70fSEmmanuel Vadot /* 12d5b0e70fSEmmanuel Vadot * cirrus,asp-sdout-hiz-ctrl 13d5b0e70fSEmmanuel Vadot * 14d5b0e70fSEmmanuel Vadot * TX_HIZ_UNUSED: TX pin high-impedance during unused slots. 15d5b0e70fSEmmanuel Vadot * TX_HIZ_DISABLED: TX pin high-impedance when all channels disabled. 16d5b0e70fSEmmanuel Vadot */ 17d5b0e70fSEmmanuel Vadot #define CS35L45_ASP_TX_HIZ_UNUSED 0x1 18d5b0e70fSEmmanuel Vadot #define CS35L45_ASP_TX_HIZ_DISABLED 0x2 19d5b0e70fSEmmanuel Vadot 20*fac71e4eSEmmanuel Vadot /* 21*fac71e4eSEmmanuel Vadot * Optional GPIOX Sub-nodes: 22*fac71e4eSEmmanuel Vadot * The cs35l45 node can have up to three "cirrus,gpio-ctrlX" ('X' = [1,2,3]) 23*fac71e4eSEmmanuel Vadot * sub-nodes for configuring the GPIO pins. 24*fac71e4eSEmmanuel Vadot * 25*fac71e4eSEmmanuel Vadot * - gpio-dir : GPIO pin direction. Valid only when 'gpio-ctrl' 26*fac71e4eSEmmanuel Vadot * is 1. 27*fac71e4eSEmmanuel Vadot * 0 = Output 28*fac71e4eSEmmanuel Vadot * 1 = Input (Default) 29*fac71e4eSEmmanuel Vadot * 30*fac71e4eSEmmanuel Vadot * - gpio-lvl : GPIO level. Valid only when 'gpio-ctrl' is 1 and 'gpio-dir' is 0. 31*fac71e4eSEmmanuel Vadot * 32*fac71e4eSEmmanuel Vadot * 0 = Low (Default) 33*fac71e4eSEmmanuel Vadot * 1 = High 34*fac71e4eSEmmanuel Vadot * 35*fac71e4eSEmmanuel Vadot * - gpio-op-cfg : GPIO output configuration. Valid only when 'gpio-ctrl' is 1 36*fac71e4eSEmmanuel Vadot * and 'gpio-dir' is 0. 37*fac71e4eSEmmanuel Vadot * 38*fac71e4eSEmmanuel Vadot * 0 = CMOS (Default) 39*fac71e4eSEmmanuel Vadot * 1 = Open Drain 40*fac71e4eSEmmanuel Vadot * 41*fac71e4eSEmmanuel Vadot * - gpio-pol : GPIO output polarity select. Valid only when 'gpio-ctrl' is 1 42*fac71e4eSEmmanuel Vadot * and 'gpio-dir' is 0. 43*fac71e4eSEmmanuel Vadot * 44*fac71e4eSEmmanuel Vadot * 0 = Non-inverted, Active High (Default) 45*fac71e4eSEmmanuel Vadot * 1 = Inverted, Active Low 46*fac71e4eSEmmanuel Vadot * 47*fac71e4eSEmmanuel Vadot * - gpio-invert : Defines the polarity of the GPIO pin if configured 48*fac71e4eSEmmanuel Vadot * as input. 49*fac71e4eSEmmanuel Vadot * 50*fac71e4eSEmmanuel Vadot * 0 = Not inverted (Default) 51*fac71e4eSEmmanuel Vadot * 1 = Inverted 52*fac71e4eSEmmanuel Vadot * 53*fac71e4eSEmmanuel Vadot * - gpio-ctrl : Defines the function of the GPIO pin. 54*fac71e4eSEmmanuel Vadot * 55*fac71e4eSEmmanuel Vadot * GPIO1: 56*fac71e4eSEmmanuel Vadot * 0 = High impedance input (Default) 57*fac71e4eSEmmanuel Vadot * 1 = Pin acts as a GPIO, direction controlled by 'gpio-dir' 58*fac71e4eSEmmanuel Vadot * 2 = Pin acts as MDSYNC, direction controlled by MDSYNC 59*fac71e4eSEmmanuel Vadot * 3-7 = Reserved 60*fac71e4eSEmmanuel Vadot * 61*fac71e4eSEmmanuel Vadot * GPIO2: 62*fac71e4eSEmmanuel Vadot * 0 = High impedance input (Default) 63*fac71e4eSEmmanuel Vadot * 1 = Pin acts as a GPIO, direction controlled by 'gpio-dir' 64*fac71e4eSEmmanuel Vadot * 2 = Pin acts as open drain INT 65*fac71e4eSEmmanuel Vadot * 3 = Reserved 66*fac71e4eSEmmanuel Vadot * 4 = Pin acts as push-pull output INT. Active low. 67*fac71e4eSEmmanuel Vadot * 5 = Pin acts as push-pull output INT. Active high. 68*fac71e4eSEmmanuel Vadot * 6,7 = Reserved 69*fac71e4eSEmmanuel Vadot * 70*fac71e4eSEmmanuel Vadot * GPIO3: 71*fac71e4eSEmmanuel Vadot * 0 = High impedance input (Default) 72*fac71e4eSEmmanuel Vadot * 1 = Pin acts as a GPIO, direction controlled by 'gpio-dir' 73*fac71e4eSEmmanuel Vadot * 2-7 = Reserved 74*fac71e4eSEmmanuel Vadot */ 75*fac71e4eSEmmanuel Vadot #define CS35L45_NUM_GPIOS 0x3 76*fac71e4eSEmmanuel Vadot 77d5b0e70fSEmmanuel Vadot #endif /* DT_CS35L45_H */ 78