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/linux/tools/perf/util/
H A Dpmus.c18 #include "pmu.h"
26 * core_pmus: A PMU belongs to core_pmus if it's name is "cpu" or it's sysfs
28 * must have pmu->is_core=1. If there are more than one PMU in
31 * homogeneous PMU, and thus they are treated as homogeneous
34 * matter whether PMU is present per SMT-thread or outside of the
38 * must have pmu->is_core=0 but pmu->is_uncore could be 0 or 1.
83 * that S390's cpum_cf PMU doesn't match. in pmu_name_len_no_suffix()
113 struct perf_pmu *pmu, *tmp; in perf_pmus__destroy() local
115 list_for_each_entry_safe(pmu, tmp, &core_pmus, list) { in perf_pmus__destroy()
116 list_del(&pmu->list); in perf_pmus__destroy()
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H A Dpmu.c22 #include "pmu.h"
28 #include <util/pmu-bison.h>
29 #include <util/pmu-flex.h>
43 /* An event loaded from /sys/bus/event_source/devices/<pmu>/events. */
48 * An event loaded from a /sys/bus/event_source/devices/<pmu>/identifier matched json
56 * pmu-events.c, created by parsing the pmu-events json files.
74 * differ from the PMU name as it won't have suffixes.
135 static int pmu_aliases_parse(struct perf_pmu *pmu);
178 static void perf_pmu_format__load(const struct perf_pmu *pmu, struct perf_pmu_format *format) in perf_pmu_format__load() argument
186 if (!perf_pmu__pathname_scnprintf(path, sizeof(path), pmu->name, "format")) in perf_pmu_format__load()
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H A Dpmu.h12 #include "pmu-events/pmu-events.h"
55 /** @name: The name of the PMU such as "cpu". */
58 * @alias_name: Optional alternate name for the PMU determined in
63 * @id: Optional PMU identifier read from
73 * @selectable: Can the PMU name be selected as if it were an event?
77 * @is_core: Is the PMU the core CPU PMU? Determined by the name being
80 * PMU on systems like Intel hybrid.
84 * @is_uncore: Is the PMU not within the CPU core? Determined by the
94 * @formats_checked: Only check PMU's formats are valid for
104 * PMU, read from
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/linux/Documentation/devicetree/bindings/soc/samsung/
H A Dexynos-pmu.yaml4 $id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml#
7 title: Samsung Exynos SoC series Power Management Unit (PMU)
18 - google,gs101-pmu
19 - samsung,exynos3250-pmu
20 - samsung,exynos4210-pmu
21 - samsung,exynos4212-pmu
22 - samsung,exynos4412-pmu
23 - samsung,exynos5250-pmu
24 - samsung,exynos5260-pmu
25 - samsung,exynos5410-pmu
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/linux/Documentation/devicetree/bindings/arm/
H A Dpmu.yaml4 $id: http://devicetree.org/schemas/arm/pmu.yaml#
14 ARM cores often have a PMU for counting cpu and cache events like cache misses
15 and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
24 - apple,blizzard-pmu
25 - apple,firestorm-pmu
26 - apple,icestorm-pmu
28 - arm,arm1136-pmu
29 - arm,arm1176-pmu
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
H A Dbase.c32 struct nvkm_pmu *pmu = device->pmu; in nvkm_pmu_fan_controlled() local
34 /* Internal PMU FW does not currently control fans in any way, in nvkm_pmu_fan_controlled()
37 if (pmu && pmu->func->code.size) in nvkm_pmu_fan_controlled()
40 /* Default (board-loaded, or VBIOS PMU/PREOS) PMU FW on Fermi in nvkm_pmu_fan_controlled()
48 nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable) in nvkm_pmu_pgob() argument
50 if (pmu && pmu->func->pgob) in nvkm_pmu_pgob()
51 pmu->func->pgob(pmu, enable); in nvkm_pmu_pgob()
57 struct nvkm_pmu *pmu = container_of(work, typeof(*pmu), recv.work); in nvkm_pmu_recv() local
58 return pmu->func->recv(pmu); in nvkm_pmu_recv()
62 nvkm_pmu_send(struct nvkm_pmu *pmu, u32 reply[2], in nvkm_pmu_send() argument
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H A Dgm20b.c28 #include <nvfw/pmu.h>
42 struct nvkm_pmu *pmu = container_of(falcon, typeof(*pmu), falcon); in gm20b_pmu_acr_bootstrap_falcon() local
52 ret = nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr, in gm20b_pmu_acr_bootstrap_falcon()
54 &pmu->subdev, msecs_to_jiffies(1000)); in gm20b_pmu_acr_bootstrap_falcon()
129 struct nvkm_pmu *pmu = priv; in gm20b_pmu_acr_init_wpr_callback() local
130 struct nvkm_subdev *subdev = &pmu->subdev; in gm20b_pmu_acr_init_wpr_callback()
139 complete_all(&pmu->wpr_ready); in gm20b_pmu_acr_init_wpr_callback()
144 gm20b_pmu_acr_init_wpr(struct nvkm_pmu *pmu) in gm20b_pmu_acr_init_wpr() argument
154 return nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr, in gm20b_pmu_acr_init_wpr()
155 gm20b_pmu_acr_init_wpr_callback, pmu, 0); in gm20b_pmu_acr_init_wpr()
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H A Dgt215.c30 gt215_pmu_send(struct nvkm_pmu *pmu, u32 reply[2], in gt215_pmu_send() argument
33 struct nvkm_subdev *subdev = &pmu->subdev; in gt215_pmu_send()
37 mutex_lock(&pmu->send.mutex); in gt215_pmu_send()
45 mutex_unlock(&pmu->send.mutex); in gt215_pmu_send()
50 * on a synchronous reply, take the PMU mutex and tell the in gt215_pmu_send()
54 pmu->recv.message = message; in gt215_pmu_send()
55 pmu->recv.process = process; in gt215_pmu_send()
65 pmu->send.base)); in gt215_pmu_send()
77 wait_event(pmu->recv.wait, (pmu->recv.process == 0)); in gt215_pmu_send()
78 reply[0] = pmu->recv.data[0]; in gt215_pmu_send()
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H A Dgk20a.c51 gk20a_pmu_dvfs_target(struct gk20a_pmu *pmu, int *state) in gk20a_pmu_dvfs_target() argument
53 struct nvkm_clk *clk = pmu->base.subdev.device->clk; in gk20a_pmu_dvfs_target()
59 gk20a_pmu_dvfs_get_cur_state(struct gk20a_pmu *pmu, int *state) in gk20a_pmu_dvfs_get_cur_state() argument
61 struct nvkm_clk *clk = pmu->base.subdev.device->clk; in gk20a_pmu_dvfs_get_cur_state()
67 gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu *pmu, in gk20a_pmu_dvfs_get_target_state() argument
70 struct gk20a_pmu_dvfs_data *data = pmu->data; in gk20a_pmu_dvfs_get_target_state()
71 struct nvkm_clk *clk = pmu->base.subdev.device->clk; in gk20a_pmu_dvfs_get_target_state()
86 nvkm_trace(&pmu->base.subdev, "cur level = %d, new level = %d\n", in gk20a_pmu_dvfs_get_target_state()
95 gk20a_pmu_dvfs_get_dev_status(struct gk20a_pmu *pmu, in gk20a_pmu_dvfs_get_dev_status() argument
98 struct nvkm_falcon *falcon = &pmu->base.falcon; in gk20a_pmu_dvfs_get_dev_status()
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/linux/drivers/soc/dove/
H A Dpmu.c3 * Marvell Dove PMU support
17 #include <linux/soc/dove/pmu.h>
42 * The PMU contains a register to reset various subsystems within the
50 struct pmu_data *pmu = rcdev_to_pmu(rc); in pmu_reset_reset() local
54 spin_lock_irqsave(&pmu->lock, flags); in pmu_reset_reset()
55 val = readl_relaxed(pmu->pmc_base + PMC_SW_RST); in pmu_reset_reset()
56 writel_relaxed(val & ~BIT(id), pmu->pmc_base + PMC_SW_RST); in pmu_reset_reset()
57 writel_relaxed(val | BIT(id), pmu->pmc_base + PMC_SW_RST); in pmu_reset_reset()
58 spin_unlock_irqrestore(&pmu->lock, flags); in pmu_reset_reset()
65 struct pmu_data *pmu = rcdev_to_pmu(rc); in pmu_reset_assert() local
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/linux/drivers/gpu/drm/i915/
H A Di915_pmu.c33 return container_of(event->pmu, struct i915_pmu, base); in event_to_pmu()
36 static struct drm_i915_private *pmu_to_i915(struct i915_pmu *pmu) in pmu_to_i915() argument
38 return container_of(pmu, struct drm_i915_private, pmu); in pmu_to_i915()
149 static bool pmu_needs_timer(struct i915_pmu *pmu) in pmu_needs_timer() argument
151 struct drm_i915_private *i915 = pmu_to_i915(pmu); in pmu_needs_timer()
159 enable = pmu->enable; in pmu_needs_timer()
201 static u64 read_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample) in read_sample() argument
203 return pmu->sample[gt_id][sample].cur; in read_sample()
207 store_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample, u64 val) in store_sample() argument
209 pmu->sample[gt_id][sample].cur = val; in store_sample()
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/linux/drivers/pmdomain/starfive/
H A Djh71xx-pmu.c3 * StarFive JH71XX PMU (Power Management Unit) Controller Driver
15 #include <dt-bindings/power/starfive,jh7110-pmu.h>
26 /* aon pmu register offset */
36 /* pmu int status */
64 struct jh71xx_pmu *pmu);
76 spinlock_t lock; /* protects pmu reg */
81 struct jh71xx_pmu *pmu; member
87 struct jh71xx_pmu *pmu = pmd->pmu; in jh71xx_pmu_get_state() local
92 *is_on = readl(pmu->base + pmu->match_data->pmu_status) & mask; in jh71xx_pmu_get_state()
99 struct jh71xx_pmu *pmu = pmd->pmu; in jh7110_pmu_set_state() local
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/linux/drivers/perf/
H A Dfsl_imx9_ddr_perf.c59 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
79 const char *identifier; /* system PMU identifier for userspace */
84 struct pmu pmu; member
112 static inline bool axi_filter_v1(struct ddr_pmu *pmu) in axi_filter_v1() argument
114 return pmu->devtype_data->filter_ver == DDR_PERF_AXI_FILTER_V1; in axi_filter_v1()
117 static inline bool axi_filter_v2(struct ddr_pmu *pmu) in axi_filter_v2() argument
119 return pmu->devtype_data->filter_ver == DDR_PERF_AXI_FILTER_V2; in axi_filter_v2()
123 { .compatible = "fsl,imx91-ddr-pmu", .data = &imx91_devtype_data },
124 { .compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data },
125 { .compatible = "fsl,imx95-ddr-pmu", .data = &imx95_devtype_data },
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H A Darm_pmu.c185 if (type == event->pmu->type) in armpmu_map_event()
202 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); in armpmu_event_set_period()
244 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); in armpmu_event_update()
274 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); in armpmu_stop()
278 * ARM pmu always has to update the counter, so ignore in armpmu_stop()
290 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); in armpmu_start()
294 * ARM pmu always has to reprogram the period, so ignore in armpmu_start()
315 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); in armpmu_del()
324 perf_sched_cb_dec(event->pmu); in armpmu_del()
337 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); in armpmu_add()
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H A Darm_pmu_platform.c25 static int probe_current_pmu(struct arm_pmu *pmu, in probe_current_pmu() argument
32 pr_info("probing PMU on CPU %d\n", cpu); in probe_current_pmu()
37 ret = info->init(pmu); in probe_current_pmu()
45 static int pmu_parse_percpu_irq(struct arm_pmu *pmu, int irq) in pmu_parse_percpu_irq() argument
48 struct pmu_hw_events __percpu *hw_events = pmu->hw_events; in pmu_parse_percpu_irq()
50 ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus); in pmu_parse_percpu_irq()
54 for_each_cpu(cpu, &pmu->supported_cpus) in pmu_parse_percpu_irq()
95 static int pmu_parse_irqs(struct arm_pmu *pmu) in pmu_parse_irqs() argument
98 struct platform_device *pdev = pmu->plat_device; in pmu_parse_irqs()
99 struct pmu_hw_events __percpu *hw_events = pmu->hw_events; in pmu_parse_irqs()
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H A DKconfig10 tristate "ARM CCI PMU driver"
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
45 tristate "Arm CMN-600 PMU support"
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
52 tristate "Arm NI-700 PMU support"
55 Support for PMU events monitoring on the Arm NI-700 Network-on-Chip
60 bool "ARM PMU framework"
80 bool "RISC-V PMU framework"
84 systems. This provides the core PMU framework that abstracts common
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/linux/arch/x86/kvm/vmx/
H A Dpmu_intel.c3 * KVM PMU support for Intel CPUs
22 #include "pmu.h"
57 static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data) in reprogram_fixed_counters() argument
60 u64 old_fixed_ctr_ctrl = pmu->fixed_ctr_ctrl; in reprogram_fixed_counters()
63 pmu->fixed_ctr_ctrl = data; in reprogram_fixed_counters()
64 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { in reprogram_fixed_counters()
71 pmc = get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i); in reprogram_fixed_counters()
73 __set_bit(KVM_FIXED_PMC_BASE_IDX + i, pmu->pmc_in_use); in reprogram_fixed_counters()
82 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); in intel_rdpmc_ecx_to_pmc() local
94 * Yell and reject attempts to read PMCs for a non-architectural PMU, in intel_rdpmc_ecx_to_pmc()
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/linux/Documentation/devicetree/bindings/arm/rockchip/
H A Dpmu.yaml4 $id: http://devicetree.org/schemas/arm/rockchip/pmu.yaml#
7 title: Rockchip Power Management Unit (PMU)
14 The PMU is used to turn on and off different power domains of the SoCs.
22 - rockchip,px30-pmu
23 - rockchip,rk3066-pmu
24 - rockchip,rk3128-pmu
25 - rockchip,rk3288-pmu
26 - rockchip,rk3368-pmu
27 - rockchip,rk3399-pmu
28 - rockchip,rk3528-pmu
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/linux/drivers/gpu/drm/xe/
H A Dxe_pmu.c20 * DOC: Xe PMU (Performance Monitoring Unit)
93 struct xe_device *xe = container_of(event->pmu, typeof(*xe), pmu.base); in event_to_gt()
101 struct xe_device *xe = container_of(event->pmu, typeof(*xe), pmu.base); in event_to_hwe()
135 struct xe_device *xe = container_of(event->pmu, typeof(*xe), pmu.base); in event_gt_forcewake()
160 static bool event_supported(struct xe_pmu *pmu, unsigned int gt_id, in event_supported() argument
163 struct xe_device *xe = container_of(pmu, typeof(*xe), pmu); in event_supported()
169 return id < sizeof(pmu->supported_events) * BITS_PER_BYTE && in event_supported()
170 pmu->supported_events & BIT_ULL(id); in event_supported()
175 struct xe_device *xe = container_of(event->pmu, typeof(*xe), pmu.base); in event_param_valid()
216 struct xe_device *xe = container_of(event->pmu, typeof(*xe), pmu.base); in xe_pmu_event_destroy()
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,dove-pinctrl.txt9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
14 Note: pmu* also allows for Power Management functions listed below
18 mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
19 mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
20 mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
21 uart1(rts), pmu*
22 mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
23 uart1(cts), lcd-spi(cs1), pmu*
24 mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu*
25 mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
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/linux/tools/perf/arch/arm/util/
H A Dpmu.c8 #include <linux/coresight-pmu.h>
15 #include "../../../util/pmu.h"
19 void perf_pmu__arch_init(struct perf_pmu *pmu) in perf_pmu__arch_init() argument
24 if (!strcmp(pmu->name, CORESIGHT_ETM_PMU_NAME)) { in perf_pmu__arch_init()
26 pmu->auxtrace = true; in perf_pmu__arch_init()
27 pmu->selectable = true; in perf_pmu__arch_init()
28 pmu->perf_event_attr_init_default = cs_etm_get_default_config; in perf_pmu__arch_init()
30 } else if (strstarts(pmu->name, ARM_SPE_PMU_NAME)) { in perf_pmu__arch_init()
31 pmu->auxtrace = true; in perf_pmu__arch_init()
32 pmu in perf_pmu__arch_init()
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/linux/arch/x86/events/intel/
H A Duncore.c139 struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu) in uncore_pmu_to_box() argument
147 return dieid < uncore_max_dies() ? pmu->boxes[dieid] : NULL; in uncore_pmu_to_box()
374 * Using uncore_pmu_event_init pmu event_init callback
381 return &box->pmu->pmu == event->pmu; in is_box_event()
391 max_count = box->pmu->type->num_counters; in uncore_collect_events()
392 if (box->pmu->type->fixed_ctl) in uncore_collect_events()
425 struct intel_uncore_type *type = box->pmu->type; in uncore_get_event_constraint()
450 if (box->pmu->type->ops->put_constraint) in uncore_put_event_constraint()
451 box->pmu->type->ops->put_constraint(box, event); in uncore_put_event_constraint()
687 * PMU if it was the only group available.
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/linux/Documentation/devicetree/bindings/perf/
H A Dapm-xgene-pmu.txt1 * APM X-Gene SoC PMU bindings
3 This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.
4 The following PMU devices are supported:
11 The following section describes the SoC PMU DT node binding.
14 - compatible : Shall be "apm,xgene-pmu" for revision 1 or
15 "apm,xgene-pmu-v2" for revision 2.
19 - reg : First resource shall be the CPU bus PMU resource.
20 - interrupts : Interrupt-specifier for PMU IRQ.
23 - compatible : Shall be "apm,xgene-pmu-l3c".
24 - reg : First resource shall be the L3C PMU resource.
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/linux/tools/perf/tests/
H A Dpmu-events.c4 #include "pmu.h"
12 #include "../pmu-events/pmu-events.h"
22 /* used for matching against events from generated pmu-events.c */
36 /* PMU which we should match against */
49 .pmu = "default_core",
60 .pmu = "default_core",
71 .pmu = "default_core",
82 .pmu = "default_core",
93 .pmu = "default_core",
104 .pmu = "default_core",
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/linux/tools/perf/pmu-events/
H A DBuild1 pmu-events-y += pmu-events.o
2 JDIR = pmu-events/arch/$(SRCARCH)
5 JDIR_TEST = pmu-events/arch/test
8 JEVENTS_PY = pmu-events/jevents.py
9 METRIC_PY = pmu-events/metric.py
10 METRIC_TEST_PY = pmu-events/metric_test.py
11 EMPTY_PMU_EVENTS_C = pmu-events/empty-pmu-events.c
12 PMU_EVENTS_C = $(OUTPUT)pmu
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