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/linux/drivers/net/ethernet/asix/
H A Dax88796c_main.h1 /* SPDX-License-Identifier: GPL-2.0-only */
21 #define TX_QUEUE_HIGH_WATER 45 /* Tx queue high water mark */
186 #define WFCR_PMEIND BIT(0) /* PME indication */
187 #define WFCR_PMETYPE BIT(1) /* PME I/O type */
188 #define WFCR_PMEPOL BIT(2) /* PME polarity */
189 #define WFCR_PMERST BIT(3) /* Reset PME */
197 #define WFCR_PMEEN BIT(11) /* Enable PME pin */
201 #define WFCR_PMES BIT(15) /* PME pin status */
217 /* Active high */
219 /* Active low */
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/linux/Documentation/arch/x86/
H A Dearlyprintk.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Mini-HOWTO for using the earlyprintk=dbgp boot option with a
13 [host/target] <-------> [USB debug key] <-------> [client/console]
21 the lspci -vvv output::
23 # lspci -vvv
25 …roller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 (rev 03) (prog-if 20 [EHCI])
27 …Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisIN…
28 …Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- I…
31 Region 0: Memory at fe227000 (32-bit, non-prefetchable) [size=1K]
33 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
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/linux/include/uapi/linux/
H A Dpci_regs.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
71 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
83 #define PCI_HEADER_TYPE_MFD 0x80 /* Multi-Function Device (possible) */
124 /* 0x35-0x3b are reserved */
130 /* Header type 1 (PCI-to-PCI bridges) */
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/linux/drivers/net/ethernet/broadcom/
H A Db44.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define DEVCTRL_MPM 0x00000040 /* Magic Packet PME Enable (B0 only) */
17 #define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */
79 #define B44_DMATX_STAT 0x020CUL /* DMA TX Current Active Desc. + Status */
83 #define DMATX_STAT_SACTIVE 0x00001000 /* State Active */
100 #define B44_DMARX_STAT 0x021CUL /* DMA RX Current Active Desc. + Status */
104 #define DMARX_STAT_SACTIVE 0x00001000 /* State Active */
125 #define B44_DMAFIFO_HI 0x0228UL /* DMA FIFO Diag High Data */
163 #define B44_CAM_DATA_HI 0x0424UL /* EMAC CAM Data High */
232 #define B44_RX_NPAUSE 0x05D8UL /* MIB RX Non-Pause Packets */
[all …]
/linux/arch/x86/pci/
H A Dfixup.c1 // SPDX-License-Identifier: GPL-2.0
3 * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
19 * i450NX -- Find and scan all secondary buses on all PXB's. in pci_fixup_i450nx()
24 dev_warn(&d->dev, "Searching for i450NX host bridges\n"); in pci_fixup_i450nx()
30 dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, in pci_fixup_i450nx()
37 pcibios_last_bus = -1; in pci_fixup_i450nx()
44 * i450GX and i450KX -- Find and scan all secondary buses. in pci_fixup_i450gx()
49 dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno); in pci_fixup_i450gx()
51 pcibios_last_bus = -1; in pci_fixup_i450gx()
63 dev_warn(&d->dev, "Fixing base address flags\n"); in pci_fixup_umc_ide()
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/linux/drivers/pci/controller/
H A Dpci-aardvark.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/irqchip/irq-msi-lib.h>
21 #include <linux/pci-ecam.h>
30 #include "../pci-bridge-emul.h"
140 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
294 writel(val, pcie->base + reg); in advk_writel()
299 return readl(pcie->base + reg); in advk_readl()
314 /* check if LTSSM is in normal operation - some L* state */ in advk_pcie_link_up()
322 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_active()
327 * reported in DL Active state. in advk_pcie_link_active()
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H A Dpci-mvebu.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
27 #include "../pci-bridge-emul.h"
40 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
130 writel(val, port->base + reg); in mvebu_writel()
135 return readl(port->base + reg); in mvebu_readl()
140 return port->io_target != -1 && port->io_attr != -1; in mvebu_has_ioport()
199 * BAR[0] -> internal registers (needed for MSI)
200 * BAR[1] -> covers all DRAM banks
201 * BAR[2] -> Disabled
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/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8060-dragonboard.dts1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/leds/common.h>
5 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
6 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
7 #include "qcom-msm8660.dtsi"
12 compatible = "qcom,apq8060-dragonboard", "qcom,msm8660";
19 stdout-path = "serial0:115200n8";
23 vph: regulator-fixed {
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/linux/drivers/net/ethernet/natsemi/
H A Dnatsemi.c3 Written/copyright 1999-2001 by Donald Becker.
23 [link no longer provides useful info -jgarzik]
62 /* Updated to recommendations in pci-skeleton v2.03. */
64 /* The user-configurable values.
72 static int debug = -1;
76 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
80 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
101 There are no ill effects from too-large receive rings. */
121 * The nic writes 32-bit values, even if the upper bytes of
122 * a 32-bit value are beyond the end of the buffer.
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/linux/Documentation/power/
H A Druntime_pm.rst5 (C) 2009-2011 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc.
18 put their PM-related work items. It is strongly recommended that pm_wq be
20 them to be synchronized with system-wide power transitions (suspend to RAM,
53 The ->runtime_suspend(), ->runtime_resume() and ->runtime_idle() callbacks
57 1. PM domain of the device, if the device's PM domain object, dev->pm_domain,
60 2. Device type of the device, if both dev->type and dev->type->pm are present.
62 3. Device class of the device, if both dev->class and dev->class->pm are
65 4. Bus type of the device, if both dev->bus and dev->bus->pm are present.
69 dev->driver->pm directly (if present).
72 priority order of callbacks from high to low is: PM domain, device type, class
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/linux/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
H A Dfwil_types.h1 // SPDX-License-Identifier: ISC
47 #define BRCMF_STA_DWDS 0x02000000 /* DWDS active */
79 #define BRCMF_OBSS_COEX_AUTO (-1)
88 /* Wakeup on loss-of-link due to Disassoc/Deauth: */
98 /* Wakeup after receipt of EAP-Identity Req: */
100 /* Wakeind via PME(0) or GPIO(1): */
255 * struct tdls_iovar - common structure for tdls iovars.
375 __le32 nprobes; /* -1 use default, number of probes per channel */
376 __le32 active_time; /* -1 use default, dwell time per channel for
377 * active scanning
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/linux/drivers/net/ethernet/intel/e1000/
H A De1000_hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
302 #define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signatu…
422 /* MAC decode size is 128K - This is the size of BAR0 */
443 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
483 /* Number of high/low register pairs in the RAR. The RAR (Receive Address
486 * E1000_RAR_ENTRIES - 1 multicast addresses.
503 /* Receive Descriptor - Extended */
529 /* Receive Descriptor - Packet Split */
553 __le16 length[3]; /* length of buffers 1-3 */
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/linux/drivers/hwmon/
H A Dit87.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * it87.c - Part of lm_sensors, Linux kernel modules for hardware
6 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
41 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
53 #include <linux/hwmon-sysfs.h>
54 #include <linux/hwmon-vid.h>
75 #define PME 0x04 /* The device with the fan registers in it */ macro
126 return -EBUSY; in superio_enter()
212 /*----- The IT87 registers -----*/
222 * Super-I/O configuration space.
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/linux/drivers/media/rc/
H A Dnuvoton-cir.c2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
32 #include <media/rc-core.h>
35 #include "nuvoton-cir.h"
48 return nvt->rdev->dev.parent; in nvt_get_dev()
53 return nvt->chip_ver == NVT_W83667HG; in is_w83667hg()
59 outb(reg, nvt->cr_efir); in nvt_cr_write()
60 outb(val, nvt->cr_efdr); in nvt_cr_write()
66 outb(reg, nvt->cr_efir); in nvt_cr_read()
67 return inb(nvt->cr_efdr); in nvt_cr_read()
80 if (!request_muxed_region(nvt->cr_efir, 2, NVT_DRIVER_NAME)) in nvt_efm_enable()
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/linux/drivers/net/ethernet/marvell/
H A Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
60 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
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/linux/drivers/net/ethernet/intel/igb/
H A De1000_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
13 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
62 /* Interrupt acknowledge Auto-mask */
118 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
184 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
186 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
254 /* Constants used to intrepret the masked PCI-X bus speed. */
271 /* 1000/H is not supported, nor spec-compliant. */
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/linux/Documentation/admin-guide/
H A Dkernel-parameters.txt16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nocmcff -- Disable firmware first mode for corrected
28 nospcr -- disable console in ACPI SPCR table as
45 If set to vendor, prefer vendor-specific driver
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/linux/drivers/pci/
H A Dpci.h1 /* SPDX-License-Identifier: GPL-2.0 */
37 * "T_PERST-CLK".
42 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
50 * - "With a Downstream Port that does not support Link speeds greater
55 * - "With a Downstream Port that supports Link speeds greater than
102 * PCI_FIND_NEXT_CAP - Find a PCI standard capability
109 * Implements TTL (time-to-live) protection against infinite loops.
122 while (__ttl--) { \
145 * PCI_FIND_NEXT_EXT_CAP - Find a PCI extended capability
164 __ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; \
[all …]
H A Dquirks.c1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
5 * should be handled in arch-specific code.
22 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */
41 if (test_bit(PCI_LINK_LBMS_SEEN, &dev->priv_flags)) in pcie_lbms_seen()
59 * link layer never reaches the active state, with link training reported
60 * repeatedly active ~84% of the time. Forcing the target link speed to
67 * Link Active status bit and in the failed link training scenario it will
73 * at least the active status.
78 * support Link Active reporting and have the Link Control 2 register.
[all …]
/linux/drivers/net/ethernet/realtek/
H A D8139cp.c3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
65 #include <linux/dma-mapping.h>
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/linux/drivers/net/ethernet/atheros/atl1e/
H A Datl1e_main.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
14 * atl1e_pci_tbl - PCI Device ID Table
76 * atl1e_irq_enable - Enable default interrupt generation settings
81 if (likely(atomic_dec_and_test(&adapter->irq_sem))) { in atl1e_irq_enable()
82 AT_WRITE_REG(&adapter->hw, REG_ISR, 0); in atl1e_irq_enable()
83 AT_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK); in atl1e_irq_enable()
84 AT_WRITE_FLUSH(&adapter->hw); in atl1e_irq_enable()
89 * atl1e_irq_disable - Mask off interrupt generation on the NIC
94 atomic_inc(&adapter->irq_sem); in atl1e_irq_disable()
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/linux/sound/pci/
H A Dcs4281.c1 // SPDX-License-Identifier: GPL-2.0-or-later
29 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
119 #define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */
123 #define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */
129 #define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */
189 #define BA0_SPMC_GIPPEN (1<<15) /* GP INT Primary PME# Enabl
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/linux/drivers/net/ethernet/via/
H A Dvia-rhine.c1 /* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
3 Written 1998-2001 by Donald Becker.
14 This driver is designed for the VIA VT86C100A Rhine-I.
15 It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
27 http://www.scyld.com/network/via-rhine.html
28 [link no longer provides useful info -jgarzik]
34 #define DRV_NAME "via-rhine"
38 /* A few user-configurable values.
44 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
54 /* Work-around for broken BIOSes: they are unable to get the chip back out of
[all …]
/linux/drivers/net/ethernet/intel/
H A De100.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
26 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
27 * configurations. 8255x supports a 32-bit linear addressing
32 * Memory-mapped mode is used exclusively to access the device's
33 * shared-memory structure, the Control/Status Registers (CSR). All
39 * 8255x is highly MII-compliant and all access to the PHY go
41 * driver leverages the mii.c library shared with other MII-compliant
44 * Big- and Little-Endian byte order as well as 32- and 64-bit
45 * archs are supported. Weak-ordered memory and non-cache-coherent
[all …]
/linux/drivers/net/ethernet/atheros/atlx/
H A Datl2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved.
4 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com>
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
12 #include <linux/dma-mapping.h>
47 * atl2_pci_tbl - PCI Device ID Table
59 * atl2_sw_init - Initialize general software structures (struct atl2_adapter)
68 struct atl2_hw *hw = &adapter->hw; in atl2_sw_init()
69 struct pci_dev *pdev = adapter->pdev; in atl2_sw_init()
72 hw->vendor_id = pdev->vendor; in atl2_sw_init()
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