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/linux/Documentation/devicetree/bindings/timer/
H A Dandestech,plmt0.yaml4 $id: http://devicetree.org/schemas/timer/andestech,plmt0.yaml#
10 The Andes machine-level timer device (PLMT0) provides machine-level timer
13 register (MTIMECMP) for each HART connected to the PLMT0. A timer interrupt is
24 - const: andestech,plmt0
33 Specifies which harts are connected to the PLMT0. Each item must points
35 PLMT0 supports 1 hart up to 32 harts.
47 compatible = "andestech,qilai-plmt", "andestech,plmt0";
/linux/arch/riscv/boot/dts/andes/
H A Dqilai.dtsi131 compatible = "andestech,qilai-plmt", "andestech,plmt0";
/linux/
H A DMAINTAINERS21653 F: Documentation/devicetree/bindings/timer/andestech,plmt0.yaml