/linux/drivers/clk/socfpga/ |
H A D | clk-pll-s10.c | 194 struct socfpga_pll *pll_clk; in s10_register_pll() local 199 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); in s10_register_pll() 200 if (WARN_ON(!pll_clk)) in s10_register_pll() 203 pll_clk->hw.reg = reg + clks->offset; in s10_register_pll() 216 pll_clk->hw.hw.init = &init; in s10_register_pll() 218 pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER; in s10_register_pll() 220 hw_clk = &pll_clk->hw.hw; in s10_register_pll() 224 kfree(pll_clk); in s10_register_pll() 234 struct socfpga_pll *pll_clk; in agilex_register_pll() local 239 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); in agilex_register_pll() [all …]
|
H A D | clk-pll.c | 78 struct socfpga_pll *pll_clk; in __socfpga_pll_init() local 87 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); in __socfpga_pll_init() 88 if (WARN_ON(!pll_clk)) in __socfpga_pll_init() 95 pll_clk->hw.reg = clk_mgr_base_addr + reg; in __socfpga_pll_init() 105 pll_clk->hw.hw.init = &init; in __socfpga_pll_init() 107 pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA; in __socfpga_pll_init() 109 hw_clk = &pll_clk->hw.hw; in __socfpga_pll_init() 129 kfree(pll_clk); in __socfpga_pll_init()
|
/linux/drivers/clk/axs10x/ |
H A D | pll_clock.c | 221 struct axs10x_pll_clk *pll_clk; in axs10x_pll_clk_probe() local 225 pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL); in axs10x_pll_clk_probe() 226 if (!pll_clk) in axs10x_pll_clk_probe() 229 pll_clk->base = devm_platform_ioremap_resource(pdev, 0); in axs10x_pll_clk_probe() 230 if (IS_ERR(pll_clk->base)) in axs10x_pll_clk_probe() 231 return PTR_ERR(pll_clk->base); in axs10x_pll_clk_probe() 233 pll_clk->lock = devm_platform_ioremap_resource(pdev, 1); in axs10x_pll_clk_probe() 234 if (IS_ERR(pll_clk->lock)) in axs10x_pll_clk_probe() 235 return PTR_ERR(pll_clk->lock); in axs10x_pll_clk_probe() 242 pll_clk->hw.init = &init; in axs10x_pll_clk_probe() [all …]
|
H A D | i2s_pll_clock.c | 170 struct i2s_pll_clk *pll_clk; in i2s_pll_clk_probe() local 173 pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL); in i2s_pll_clk_probe() 174 if (!pll_clk) in i2s_pll_clk_probe() 177 pll_clk->base = devm_platform_ioremap_resource(pdev, 0); in i2s_pll_clk_probe() 178 if (IS_ERR(pll_clk->base)) in i2s_pll_clk_probe() 179 return PTR_ERR(pll_clk->base); in i2s_pll_clk_probe() 188 pll_clk->hw.init = &init; in i2s_pll_clk_probe() 189 pll_clk->dev = dev; in i2s_pll_clk_probe() 191 clk = devm_clk_register(dev, &pll_clk->hw); in i2s_pll_clk_probe()
|
/linux/drivers/clk/ |
H A D | clk-hsdk-pll.c | 310 struct hsdk_pll_clk *pll_clk; in hsdk_pll_clk_probe() local 314 pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL); in hsdk_pll_clk_probe() 315 if (!pll_clk) in hsdk_pll_clk_probe() 318 pll_clk->regs = devm_platform_ioremap_resource(pdev, 0); in hsdk_pll_clk_probe() 319 if (IS_ERR(pll_clk->regs)) in hsdk_pll_clk_probe() 320 return PTR_ERR(pll_clk->regs); in hsdk_pll_clk_probe() 333 pll_clk->hw.init = &init; in hsdk_pll_clk_probe() 334 pll_clk->dev = dev; in hsdk_pll_clk_probe() 335 pll_clk->pll_devdata = of_device_get_match_data(dev); in hsdk_pll_clk_probe() 337 if (!pll_clk->pll_devdata) { in hsdk_pll_clk_probe() [all …]
|
H A D | clk-vt8500.c | 688 struct clk_pll *pll_clk; in vtwm_pll_clk_init() local 701 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); in vtwm_pll_clk_init() 702 if (WARN_ON(!pll_clk)) in vtwm_pll_clk_init() 705 pll_clk->reg = pmc_base + reg; in vtwm_pll_clk_init() 706 pll_clk->lock = &_lock; in vtwm_pll_clk_init() 707 pll_clk->type = pll_type; in vtwm_pll_clk_init() 718 pll_clk->hw.init = &init; in vtwm_pll_clk_init() 720 hw = &pll_clk->hw; in vtwm_pll_clk_init() 721 rc = clk_hw_register(NULL, &pll_clk->hw); in vtwm_pll_clk_init() 723 kfree(pll_clk); in vtwm_pll_clk_init()
|
H A D | clk-moxart.c | 59 struct clk *pll_clk; in moxart_of_apb_clk_init() local 81 pll_clk = of_clk_get(node, 0); in moxart_of_apb_clk_init() 82 if (IS_ERR(pll_clk)) { in moxart_of_apb_clk_init()
|
/linux/arch/sh/kernel/cpu/sh2a/ |
H A D | clock-sh7269.c | 47 static struct clk pll_clk = { variable 64 .parent = &pll_clk, 79 .parent = &pll_clk, 86 &pll_clk, 106 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 142 CLKDEV_CON_ID("pll_clk", &pll_clk),
|
H A D | clock-sh7264.c | 51 static struct clk pll_clk = { variable 60 &pll_clk, 78 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 108 CLKDEV_CON_ID("pll_clk", &pll_clk),
|
/linux/drivers/spi/ |
H A D | spi-bcmbca-hsspi.c | 117 struct clk *pll_clk; member 439 struct clk *clk, *pll_clk = NULL; in bcmbca_hsspi_probe() local 465 pll_clk = devm_clk_get(dev, "pll"); in bcmbca_hsspi_probe() 467 if (IS_ERR(pll_clk)) { in bcmbca_hsspi_probe() 468 ret = PTR_ERR(pll_clk); in bcmbca_hsspi_probe() 472 ret = clk_prepare_enable(pll_clk); in bcmbca_hsspi_probe() 476 rate = clk_get_rate(pll_clk); in bcmbca_hsspi_probe() 492 bs->pll_clk = pll_clk; in bcmbca_hsspi_probe() 564 clk_disable_unprepare(pll_clk); in bcmbca_hsspi_probe() 577 clk_disable_unprepare(bs->pll_clk); in bcmbca_hsspi_remove() [all …]
|
H A D | spi-bcm63xx-hsspi.c | 136 struct clk *pll_clk; member 730 struct clk *clk, *pll_clk = NULL; in bcm63xx_hsspi_probe() local 764 pll_clk = devm_clk_get(dev, "pll"); in bcm63xx_hsspi_probe() 766 if (IS_ERR(pll_clk)) { in bcm63xx_hsspi_probe() 767 ret = PTR_ERR(pll_clk); in bcm63xx_hsspi_probe() 771 ret = clk_prepare_enable(pll_clk); in bcm63xx_hsspi_probe() 775 rate = clk_get_rate(pll_clk); in bcm63xx_hsspi_probe() 791 bs->pll_clk = pll_clk; in bcm63xx_hsspi_probe() 874 clk_disable_unprepare(pll_clk); in bcm63xx_hsspi_probe() 888 clk_disable_unprepare(bs->pll_clk); in bcm63xx_hsspi_remove() [all …]
|
/linux/drivers/clk/renesas/ |
H A D | rzv2h-cpg.c | 105 struct pll_clk { struct 111 #define to_pll(_hw) container_of(_hw, struct pll_clk, hw) argument 173 struct pll_clk *pll_clk = to_pll(hw); in rzv2h_cpg_pll_clk_is_enabled() local 174 struct rzv2h_cpg_priv *priv = pll_clk->priv; in rzv2h_cpg_pll_clk_is_enabled() 175 u32 val = readl(priv->base + CPG_PLL_MON(pll_clk->pll.offset)); in rzv2h_cpg_pll_clk_is_enabled() 184 struct pll_clk *pll_clk = to_pll(hw); in rzv2h_cpg_pll_clk_enable() local 185 struct rzv2h_cpg_priv *priv = pll_clk->priv; in rzv2h_cpg_pll_clk_enable() 186 struct pll pll = pll_clk->pll; in rzv2h_cpg_pll_clk_enable() 222 struct pll_clk *pll_clk = to_pll(hw); in rzv2h_cpg_pll_clk_recalc_rate() local 223 struct rzv2h_cpg_priv *priv = pll_clk->priv; in rzv2h_cpg_pll_clk_recalc_rate() [all …]
|
H A D | rzg2l-cpg.c | 955 struct pll_clk { struct 964 #define to_pll(_hw) container_of(_hw, struct pll_clk, hw) argument 969 struct pll_clk *pll_clk = to_pll(hw); in rzg2l_cpg_pll_clk_recalc_rate() local 970 struct rzg2l_cpg_priv *priv = pll_clk->priv; in rzg2l_cpg_pll_clk_recalc_rate() 974 if (pll_clk->type != CLK_TYPE_SAM_PLL) in rzg2l_cpg_pll_clk_recalc_rate() 977 val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf)); in rzg2l_cpg_pll_clk_recalc_rate() 978 val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf)); in rzg2l_cpg_pll_clk_recalc_rate() 993 struct pll_clk *pll_clk = to_pll(hw); in rzg3s_cpg_pll_clk_recalc_rate() local 994 struct rzg2l_cpg_priv *priv = pll_clk->priv; in rzg3s_cpg_pll_clk_recalc_rate() 998 if (pll_clk->type != CLK_TYPE_G3S_PLL) in rzg3s_cpg_pll_clk_recalc_rate() [all …]
|
/linux/arch/sh/kernel/cpu/sh4a/ |
H A D | clock-sh7722.c | 82 static struct clk pll_clk = { variable 91 &pll_clk, 109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 138 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), 174 CLKDEV_CON_ID("pll_clk", &pll_clk), 226 pll_clk.parent = &dll_clk; in arch_clk_init() 228 pll_clk.parent = &extal_clk; in arch_clk_init()
|
H A D | clock-sh7757.c | 37 static struct clk pll_clk = { variable 45 &pll_clk, 63 SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags) 105 CLKDEV_CON_ID("pll_clk", &pll_clk),
|
H A D | clock-shx3.c | 36 static struct clk pll_clk = { variable 44 &pll_clk, 62 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) 103 CLKDEV_CON_ID("pll_clk", &pll_clk),
|
H A D | clock-sh7343.c | 76 static struct clk pll_clk = { variable 85 &pll_clk, 106 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 122 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), 190 CLKDEV_CON_ID("pll_clk", &pll_clk), 258 pll_clk.parent = &dll_clk; in arch_clk_init() 260 pll_clk.parent = &extal_clk; in arch_clk_init()
|
H A D | clock-sh7366.c | 79 static struct clk pll_clk = { variable 88 &pll_clk, 109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 125 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), 188 CLKDEV_CON_ID("pll_clk", &pll_clk), 251 pll_clk.parent = &dll_clk; in arch_clk_init() 253 pll_clk.parent = &extal_clk; in arch_clk_init()
|
H A D | clock-sh7723.c | 83 static struct clk pll_clk = { variable 92 &pll_clk, 112 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 138 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), 199 CLKDEV_CON_ID("pll_clk", &pll_clk), 274 pll_clk.parent = &dll_clk; in arch_clk_init() 276 pll_clk.parent = &extal_clk; in arch_clk_init()
|
H A D | clock-sh7785.c | 40 static struct clk pll_clk = { variable 48 &pll_clk, 67 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) 119 CLKDEV_CON_ID("pll_clk", &pll_clk),
|
H A D | clock-sh7724.c | 85 static struct clk pll_clk = { variable 102 .parent = &pll_clk, 119 &pll_clk, 151 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 264 CLKDEV_CON_ID("pll_clk", &pll_clk), 348 pll_clk.parent = &fll_clk; in arch_clk_init() 350 pll_clk.parent = &extal_clk; in arch_clk_init()
|
H A D | clock-sh7786.c | 42 static struct clk pll_clk = { variable 50 &pll_clk, 68 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) 128 CLKDEV_CON_ID("pll_clk", &pll_clk),
|
H A D | clock-sh7734.c | 42 static struct clk pll_clk = { variable 50 &pll_clk, 70 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 181 CLKDEV_CON_ID("pll_clk", &pll_clk),
|
/linux/drivers/clk/ti/ |
H A D | fapll.c | 496 struct clk *pll_clk) in ti_fapll_synth_setup() argument 521 synth->clk_pll = pll_clk; in ti_fapll_synth_setup() 543 struct clk *pll_clk; in ti_fapll_setup() local 599 pll_clk = clk_register(NULL, &fd->hw); in ti_fapll_setup() 600 if (IS_ERR(pll_clk)) in ti_fapll_setup() 603 fd->outputs.clks[0] = pll_clk; in ti_fapll_setup() 642 output_name, name, pll_clk); in ti_fapll_setup()
|
/linux/drivers/clk/samsung/ |
H A D | clk-pll.c | 1453 const struct samsung_pll_clock *pll_clk) in _samsung_clk_register_pll() argument 1462 __func__, pll_clk->name); in _samsung_clk_register_pll() 1466 init.name = pll_clk->name; in _samsung_clk_register_pll() 1467 init.flags = pll_clk->flags; in _samsung_clk_register_pll() 1468 init.parent_names = &pll_clk->parent_name; in _samsung_clk_register_pll() 1471 if (pll_clk->rate_table) { in _samsung_clk_register_pll() 1473 for (len = 0; pll_clk->rate_table[len].rate != 0; ) in _samsung_clk_register_pll() 1477 pll->rate_table = kmemdup_array(pll_clk->rate_table, in _samsung_clk_register_pll() 1483 __func__, pll_clk->name); in _samsung_clk_register_pll() 1486 switch (pll_clk->type) { in _samsung_clk_register_pll() [all …]
|